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1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
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1.5.3. Parameter Settings
GUI Name | Legal Value in GUI | Description |
---|---|---|
Which operation mode will you be using? | REMOTE | Specifies the configuration mode of the Remote Update Intel® FPGA IP core. |
Which configuration device will you be using? |
|
Choose the configuration device that you are using. |
Add support for writing configuration parameters | — | Enable this if you need to write configuration parameters. |
Enable reconfig POF checking | — | Allows you to enable .pof checking, which allows the remote update block to verify the existence of an application configuration image before the image is loaded. When you turn on this parameter, the Remote Update Intel® FPGA IP core checks the .pof and sends the reconfig signal. This option is disabled by default. |