Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Arria® 10 and Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Arria® 10 and Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.7.2. Cyclone® V Remote Update Design Example

Intel® uses the following hardware and software to create the design example:

  • Quartus® Prime Version: 13.0
  • Cyclone® V Development Kit with 5CEFA7F31C7ES FPGA Device

Follow these steps to perform the design example tasks:

  1. Unzip the contents of the design example to your working directory on your PC.
  2. In the Quartus® Prime software, click Open Project in the File menu.
  3. Compile the application image:
    1. Browse to the folder in which you unzipped the files and open the Application_Image.qpf.
    2. Click Yes in the message box "Do you want to overwrite the database for C:/your working directory/Application_Image.qpf created by Quartus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"
    3. On the Processing menu, choose Start Compilation.
    4. Click OK when the full compilation successful dialog box appears. The Application_Image.sof is generated in c:\<your working directory>\output_files.
    5. Click close project in the file menu.
  4. Compile the factory image:
    1. Browse to the folder in which you unzipped the files and open the SVRSU.qpf.
    2. Click Yes in the message box "Do you want to overwrite the database for C:/your working directory/Application_Image.qpf created by Quartus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"
    3. Choose Start Compilation on the Processing menu.
    4. Click OK when the full compilation successful dialog box appears. The Factory_Image.sof is generated in c:\<your working directory>\output_files.
  5. On the File Menu, click Convert Programming Files and select the details as shown below:
    • Programming File type: JTAG Indirect Configuration File (.jic)
    • Select Configuration Device: EPCQ 128
    • Mode: Active Serial x4
    • File name: c:/<your working directory>/output_file.jic
    • Flash loader: click add device and choose 5CEFA7ES
    • SOFT DATA PAGE_0: click Add File and select the factory image file (SVRSU.sof)
    • SOFT DATA PAGE_1: click Add File and select the Application image file (Application_Image.sof)
    • Click Generate.
    • Click OK when the dialog box of .jic file successfully generated appears.
  6. On the Tool Menu, click Programmer and follow these steps:
    1. Make sure the board is power up and the Intel® FPGA Download Cable is connected between computer and the board. This design example uses the Intel® FPGA Download Cable and JTAG mode.
    2. Click Auto Detect.
    3. Right-click on the 5CEFA7ES and select change file.
    4. Browse to the output_file.jic that was generated in previous steps.
    5. Turn on the Program/Configure checkbox and click Start.
    6. Configuration successful indicates the FPGA is configured successfully.
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