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1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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6.4. Transceiver Reconfiguration Signals
You access the transceiver control and status registers using the transceiver reconfiguration interface. This is an Avalon® memory-mapped interface.
The Avalon® memory-mapped interface implements a standard memory-mapped protocol. You can connect an Avalon® master to this bus to access the registers of the embedded Transceiver PHY IP core.
Port Name | Direction | Description |
---|---|---|
reconfig_clk | Input | Avalon® clock. The clock frequency is 100- 161 MHz. All signals transceiver reconfiguration interface signals are synchronous to reconfig_clk . |
reconfig_reset | Input | Resets the Avalon® memory-mapped interface and all of the registers to which it provides access. |
reconfig_write | Input | Write enable signal. Signal is active high. |
reconfig_read | Input | Read enable signal. Signal is active high. |
reconfig_address[ 12 :0] | Input | Address bus. |
reconfig_writedata[31:0] | Input | A 32-bit data write bus. reconfig_address specifies the address. |
reconfig_readdata[31:0] | Output | A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted. |
reconfig_waitrequest | Output | Indicates the Avalon® memory-mapped interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted. |
Note: This IP internally implements the auto adaptation triggering for RX PMA CTLE/DFE mode.
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