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1. About the Low Latency 40G Ethernet Core
2. Stratix® 10 Low Latency 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Stratix® 10 Low Latency 40G Ethernet IP Core and Low Latency 40G Ethernet IP Core That Targets an Arria 10 Device
12. Document Revision History for Stratix® 10 Low Latency 40G Ethernet User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Stratix® 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Stratix® 10 Low Latency 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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6.7. Reset Signals
The IP core has three external hard reset inputs. These resets are asynchronous and are internally synchronized. Assert resets for ten cycles or until you observe the effect of their specific reset. Asserting the external hard reset csr_rst_n returns control and status registers to their original values, with the exception of the statistics counters. rx_pcs_ready and tx_lanes_stable are asserted when the IP core has exited reset successfully.
Signal |
Direction |
Description |
---|---|---|
tx_rst_n | Input | Active low hard reset signal. Resets the TX interface, including the TX PCS and TX MAC. This reset leads to the deassertion of the tx_lanes_stable output signal. |
rx_rst_n | Input | Active low hard reset signal. Resets the RX interface, including the RX PCS and RX MAC. This reset leads to the deassertion of the rx_pcs_ready output signal. |
csr_rst_n | Input | Active low hard global reset. Resets the full IP core. Resets the TX MAC, RX MAC, TX PCS, RX PCS, transceivers, and control and status registers, except the statistics counters. This reset leads to the deassertion of the tx_lanes_stable and rx_pcs_ready output signals. |
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