Low Latency 40-Gbps Ethernet Intel® FPGA IP User Guide: Stratix® 10

ID 683600
Date 5/31/2024
Public

Visible to Intel only — GUID: ewo1451333691981

Ixiasoft

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3.5.5. Placement Settings for the Stratix® 10 Low Latency 40G Ethernet Core

The Quartus Prime software provides the options to specify design partitions and Logic Lock (Standard) or Logic Lock regions for incremental compilation, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.

The appropriate floorplan is always design-specific, and depends on your design.