Visible to Intel only — GUID: gtz1586985759022
Ixiasoft
Visible to Intel only — GUID: gtz1586985759022
Ixiasoft
6.9. Flow Control Interface
Signal Name |
Direction |
Description |
---|---|---|
pause_insert_tx0[(FCQN-1):0] pause_insert_tx1[(FCQN-1):0] |
Input | This signal is available if you specify pause on PFC.
The signal indicates to the MAC whether XON or XOFF Pause or PFC flow control frame should be sent.
1-bit mode request model: The IP core ignores pause_insert_tx1[(FCQN-1):0].
The following encoding is defined:
2-bit mode request model: The higher-order bit is in pause_insert_tx1[(FCQN-1):0] and the lower-order bit is in pause_insert_tx0[(FCQN-1):0]. The XON/XOFF request is a level-based request. The following encoding is defined:
|
pause_receive_rx[(FCQN-1):0] | Output | Each pause_receive_rx[(FCQN-1):0] bit indicates the corresponding queue is being paused. This is a level-based signal. |