LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520
Date 9/20/2022
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LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Initialization and Reset x
Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES Intel® FPGA IP Parameter Settings x
LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES Intel® FPGA IP Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES Intel® FPGA IP Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES Intel® FPGA IP Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES Intel® FPGA IP Design Examples x
LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

IOPLL Parameter Values for External PLL Mode

These examples show the clocking requirements to generate output clocks for LVDS SERDES IP using the IOPLL IP. The examples set the phase shift with the assumption that the clock and data are edge-aligned at the pins of the device.
Note: For other clock and data phase relationships, Intel recommends that you first instantiate your LVDS SERDES IP interface without using the external PLL mode option. Compile the IPs in the Intel® Quartus® Prime software and take note of the frequency, phase shift, and duty cycle settings for each clock output. Enter these settings in the IOPLL IP parameter editor and then connect the appropriate output to the LVDS SERDES IPs.
Table 22.  Example: Generating Output Clocks Using an IOPLL IP (Receiver in Non-DPA Mode)This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate three output clocks using an IOPLL IP if you are using the non-DPA receiver.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP transmitter or receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP transmitter or receiver)

outclk2

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor
Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

0°
Duty cycle

50%

 100/serialization factor

50%

The calculations for phase shift, using the RSKM equation, assume that the input clock and serial data are edge aligned. Introducing a phase shift of 180° to sampling clock (outclk0) ensures that the input data is center-aligned with respect to the outclk0, as shown in the following figure.

Figure 17. Phase Relationship for External PLL Interface Signals


Table 23.  Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode)This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate four output clocks using an IOPLL IP if you are using the DPA or soft-CDR receiver. The locked output port of IOPLL IP must be inverted and connected to the pll_areset port of the LVDS SERDES IP if you are using the DPA or soft-CDR receiver.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP transmitter or receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP transmitter or receiver)

Not required for the soft-CDR receiver.

outclk2

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

VCO Frequency

(Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

data rate
Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

0°

—
Duty cycle

50%

 100/serialization factor

50%

—
Table 24.   Example: Generating Output Clocks Using a Shared IOPLL IP for Transmitter Spanning Multiple Banks Shared with Receiver Channels (Receiver in DPA or Soft-CDR Mode) This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate six output clocks using an IOPLL IP. Use these settings if you use transmitter channels that span multiple banks shared with receiver channels in DPA or soft-CDR mode. The locked output port of IOPLL IP must be inverted and connected to the pll_areset port of the LVDS SERDES IP if you are using the DPA or soft-CDR mode.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP receiver)

Not required for the soft-CDR receiver.

outclk4

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

VCO Frequency

(Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP)

outclk2

(Connects as lvds_clk[1] to the ext_fclk port of LVDS SERDES IP transmitter)

outclk3

(Connects as loaden[1] to the ext_loaden port of LVDS SERDES IP transmitter)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

data rate
Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

0°

—
Duty cycle

50%

 100/serialization factor

50%

—
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