Visible to Intel only — GUID: kmd1508488935821
Ixiasoft
Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: kmd1508488935821
Ixiasoft
Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
Figure 18. Non-DPA LVDS Receiver Interface with IOPLL IP in External PLL Mode
Figure 19. DPA LVDS Receiver Interface with the IOPLL IP in External PLL ModeInvert the locked output port and connect it to the pll_areset port.
Figure 20. Soft-CDR LVDS Receiver Interface with the IOPLL IP in External PLL ModeInvert the locked output port and connect it to the pll_areset port.
Figure 21. LVDS Transmitter Interface with the IOPLL IP in External PLL ModeConnect the I/O PLL lvds_clk[1] and loaden[1] ports to the ext_fclk and ext_loaden ports of the LVDS transmitter.
The ext_coreclock port is automatically enabled in the LVDS SERDES IP in external PLL mode. The Intel® Quartus® Prime compiler outputs error messages if this port is not connected as shown in the preceding figures.