Visible to Intel only — GUID: sam1403482511865
Ixiasoft
Visible to Intel only — GUID: sam1403482511865
Ixiasoft
IOPLL IP Signal Interface with LVDS SERDES IP
From the IOPLL IP | To the LVDS SERDES IP Transmitter | To the LVDS SERDES IP Receiver |
---|---|---|
lvds_clk[0] (serial clock output signal)
The serial clock output can only drive ext_fclk on the LVDS SERDES IP transmitter and receiver. This clock cannot drive the core logic. |
ext_fclk (serial clock input to the transmitter) |
ext_fclk (serial clock input to the receiver) |
loaden[0] (load enable output)
|
ext_loaden (load enable to the transmitter) |
ext_loaden (load enable for the deserializer) This signal is not required for LVDS receiver in soft-CDR mode. |
outclk2 (parallel clock output) |
ext_coreclock (parallel core clock) |
ext_coreclock (parallel core clock) |
locked |
— | pll_areset (asynchronous PLL reset port) |
phout[7:0]
|
— | ext_vcoph This signal is required only for LVDS receiver in DPA or soft-CDR mode. |