R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/26/2023
Public

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Document Table of Contents

2.2.2. Reset

Follow the guidelines below for a proper reset implementation for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express:
  • The pin_perst_n signal affects the entire R-Tile. Toggling pin_perst_n will affect all the active cores.
  • When using the Configuration Mode 1 (2x8 Endpoint only) and based on the OPN used in the Intel Quartus project, you have the additional PERST# pins: pin_perst0 and pin_perst1, to independently reset port 0 and port 1 respectively. Refer to section Independent PERST pin for additional information and the OPNs that support this feature.

    Note: Refer to the Intel Agilex® 7 Device Family Pin Connection Guidelines for additional details on the correct implementation and usage of pin_perst0 and pin_perst1.

  • The pin_perst_n signal must qualify that both refclk0 and refclk1 are stable, when using the following Configuration Modes:
    • Configuration Mode 0 (1x16)
    • Configuration Mode 1 (2x8) with the parameter Enable Independent perst pins set to disabled
    • Configuration Mode 2 (4x4)

    In case one of the reference clocks becomes stable later, deassert pin_perst_n after this reference clock becomes stable.

  • The pin_perst0 must qualify the refclk0 stability, and pin_perst1 must qualify the refclk1 stability when using Configuration Mode 1 (2x8 Endpoint only) with the parameter Enable Independent perst pins set to enabled.
  • pin_perst_n assertion is required for the Autonomous mode functionality in the R-Tile Avalon® Streaming Intel® FPGA IP for PCIe. In Autonomous mode (enabled by default), the IP can successfully link up upon the release of pin_perst_n regardless of the FPGA fabric configuration and will send out Completion TLPs with the Configuration Retry Status (CRS) set until the FPGA fabric is configured and ready.
  • pin_perst_n assertion should be avoided during a functional-level reset or before a functional-level reset is completed since this could impact the link training process. In case this occurs, a cold reset would be required to properly complete the link training process.
  • The pX_reset_status_n_o signal from the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express includes an accumulative characteristic related to the number of back-to-back pin_perst_n assertions. Each back-to-back pin_perst_n event will be queued and executed one after the other, affecting the total time it takes for the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express to come out of reset and deassert the pX_reset_status_n_o signal. For additional information on the pX_reset_status_n_o signal, refer to Resets.