R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.4.1. Using the Hard IP Reconfiguration Interface to Enable and Read ECRC and LCRC Error Counts

Offset Bit Positions Register
x16 x8 x4
0x0000_0119 0x0000_0119 0x0000_0119 [0]

Register: AER_CAP/ADV_ERR_CAP_CTRL_OFF

Field: ECRC_CHECK_EN

0x0000_036C 0x0000_032C 0x0000_02D4 [1:0] Set to 2'b11 to clear the counters.
[4:2] Set to 3'b111 to enable the counters.
0x0000_036D 0x0000_032D 0x0000_02D5 [7:0] Set to 0x00. Reserved.
0x0000_036E 0x0000_032E 0x0000_02D6 [7:0]

Event Number.

For LCRC error count, set to 0x01.

For ECRC error count, set to 0x02.

0x0000_036F 0x0000_032F 0x0000_02D7 [7:0]

Group Number.

For LCRC error count, set to 0x02.

For ECRC error count, set to 0x03.

0x0000_0370 0x0000_0330 0x0000_02D8 [7:0] Error counter data bits [7:0].
0x0000_0371 0x0000_0331 0x0000_02D9 [7:0] Error counter data bits [15:8].
0x0000_0372 0x0000_0332 0x0000_02DA [7:0] Error counter data bits [23:16].
0x0000_0373 0x0000_0333 0x0000_02DB [7:0] Error counter data bits [31:24].

Follow the steps below to access registers in the table above using the Hard IP reconfiguration interface:

  1. Enable the Hard IP reconfiguration interface using the IP Parameter Editor.
  2. Enable CRC checking in the register AER_CAP/ADV_ERR_CAP_CTRL_OFF.
  3. Set the group number and event number.
  4. Enable the counters.
  5. Read the counter data.

Below is an example to enable the counter for the LCRC:

  1. Enable the Hard IP reconfiguration interface using the IP Parameter Editor.
  2. Enable CRC checking by performing a read-modify-write to the ECRC_CHECK_EN field within the register AER_CAP/ADV_ERR_CAP_CTRL_OFF.
    1. p0_hip_reconfig_write = 1’b1
    2. p0_hip_reconfig_address[31:0] = 0x0000_0119
    3. p0_hip_reconfig_writedata[7:0] = 8'h01
  3. Perform read-modify-write to address 0x0000_036F to set Group Number to 0x2.
    1. p0_hip_reconfig_write = 1’b1
    2. p0_hip_reconfig_address[31:0] = 0x0000_036F
    3. p0_hip_reconfig_writedata[7:0] = 8'h02
  4. Perform read-modify-write to address 0x0000_036E to set Event Number to 0x1.
    1. p0_hip_reconfig_write = 1’b1
    2. p0_hip_reconfig_address[31:0] = 0x0000_036E
    3. p0_hip_reconfig_writedata[7:0] = 8'h01
  5. Perform read-modify-write to address 0x0000_036D with 0x0.
    1. p0_hip_reconfig_write = 1’b1
    2. p0_hip_reconfig_address[31:0] = 0x0000_036D
    3. p0_hip_reconfig_writedata[7:0] = 8'h00
  6. Perform read-modify-write to address 0x0000_036C to set Enable Event Counter.
    1. p0_hip_reconfig_write = 1’b1
    2. p0_hip_reconfig_address[31:0] = 0x0000_036C
    3. p0_hip_reconfig_writedata[7:0] = 8'h1C
  7. Read the error counter data by performing a read operation from registers 0x0000_0370, 0x0000_0371, 0x0000_0372, and 0x0000_0373.