2.2.1. Clocking

R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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Date 6/26/2023

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2.2.1. Clocking

In the PCIe Hard IP mode, the R-Tile Avalon Streaming Intel FPGA IP for PCI Express* has four primary clock domains:

PHY clock domain (i.e. core_clk domain): this clock is synchronous to the SerDes parallel clock.
EMIB/FPGA fabric interface clock domain (i.e. pld_clk domain): this clock is derived depending on the OPN being used and the parameter Enable Independent perst pins. If this parameter is set to disabled, this clock is derived from refclk0. On the other hand, if Enable Independent perst pins is set to enabled, this clock is derived from refclk2. Refer to the Intel Agilex® 7 Device Family Pin Connection Guidelines for further details on the implementation of the refclk pins available for your specific OPN.
Application clock domain (coreclkout_hip) for in-band signals: this clock is an output from the R-Tile IP, and it has the same frequency as pld_clk.
Application clock domain (slow_clk) for sideband signals: this clock is another output from the R-Tile IP. It is a divide-by-2/4 version of coreclkout_hip.

Figure 2. Clock Domains in PCIe Modes

Table 10. PHY Clock and Application Clock Frequencies
Mode	PHY Clock Frequency	Application Clock Frequency
PCIe Gen1	1000 MHz	Gen1 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz - 300 MHz.
PCIe Gen2	1000 MHz	Gen2 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz - 300 MHz.
PCIe Gen3	1000 MHz	250 MHz - 500 MHz (*)
PCIe Gen4	1000 MHz	250 MHz - 500 MHz (*)
PCIe Gen5	1000 MHz	400 MHz - 500 MHz

Note:

(*) The highest frequencies at Gen3 and Gen4 for the Application Clock Frequency are only available in the following OPNs:

AGIx027R29AxxxxR2
AGIx027R29AxxxxR3
AGIx027R29BxxxxR3
AGIx023R18AxxxxR0
AGIx041R29DxxxxR0
AGIx041R29DxxxxR1

For additional details, refer to the Available Options section of the Intel Agilex® 7 FPGAs and SoCs Device Overview.

Note: For a link down-training scenario when R-Tile is configured at Gen3, Gen4 or Gen5 and the link gets down-trained to a lower speed, the application clock frequency will continue to run at the configured frequency set in the PLD Clock Frequency parameter. For example, when the PCIe Hard IP Mode parameter is set as Gen5 1x16 and the PLD Clock Frequency parameter as 500 MHz, the PLD clock frequency will continue to run at 500 MHz even if the link is down-trained to Gen4 or less.

R-Tile may have up to three reference clock inputs at the package level, refclk0, refclk1, and refclk2, depending on the OPN being used. Refer to the Intel Agilex® 7 Device Family Pin Connection Guidelines for further details on the implementation of the refclk pins available for your specific OPN.

The connection requirements for these input clocks depend on the Configuration mode being used and the Enable Independent perst pins parameter. You must consider the following guidelines:

Connect a 100 MHz reference clock source to refclk0 and refclk1.
If using Configuration Mode 0 (1x16) or Configuration Mode 2 (4x4), drive refclk0 and refclk1 using a single clock source.

Figure 3. Using a Single 100 MHz Clock Source in 1x16 and 4x4 Modes

In Configuration Mode 1 (2x8), you can drive the refclk0 and refclk1 inputs with either a single 100 MHz clock source as shown above, or two independent 100 MHz sources (see Using Independent 100 MHz Clock Sources in 2x8 Mode) depending on your system architecture. For example, if your system has each x8 port connected to a separate CPU/Root Complex, it may be required to drive these refclk inputs using independent clock sources. In that case, if the parameter Enable Independent perst pins is set to disabled, the refclk0 input for Port 0 must always be running because it feeds the reference clock for the R-Tile core PLL that controls the data transfers between the R-Tile and FPGA fabric via the EMIB. If this clock goes down, Port 0 link will go down and Port 1 will not be able to communicate with the FPGA fabric.

On the other hand, if the parameter Enable Independent perst pins is set to enabled, the refclk2 input must always be running because it feeds the R-Tile core PLL that controls the data transfers between the R-Tile and FPGA fabric via the EMIB.

Following are the guidelines for implementing two independent refclks in Configuration Mode 1 (2x8) with the parameter Enable Independent perst pins set to disabled:

If the link can handle two separate reference clocks, drive the refclk0 of R-Tile with the on-board free-running oscillator.
If the link needs to use a common reference clock, then PERST# needs to indicate the stability of this reference clock. If this reference clock goes down, the entire R-Tile must be reset.

Following are the guidelines for implementing two independent refclks in Configuration Mode 1 (2x8) with the parameter Enable Independent perst pins set to enabled:

Drive the additional refclk2 of R-Tile with an on-board free-running oscillator.
The pin pin_perst_n indicates the stability of this reference clock. If this reference clock goes down, the entire R-Tile must be reset.

Figure 4. Using Independent 100 MHz Clock Sources in 2x8 Mode

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R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

2.2.1. Clocking