R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/26/2023
Public

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2.2.2.2. Independent PERST Pins

Depending on the OPN being used, the R-Tile Avalon Streaming Intel FPGA IP for PCIe allows the flexibility to handle the independent reset operation for each of the active PCIe cores when Configuration Mode 1 (2x8 Endpoint only) is selected. For more information on the Configuration Modes, refer to Configuration Modes Supported by the R-Tile Avalon Streaming Intel FPGA IP for PCI Express.

The OPNs that support the additional independent PERST pins at the package level are: AGI*041R29D*R1 (for example, AGIB041R29D1E2VR1).

When you enable the Enable Independent Perst pins parameter in the IP Parameter Editor, the additional pin_perst0_n, pin_perst1_n at the package level must be used. In addition, the pX_warm_pest_n_i optional ports become available.

Consider the following guidelines for handling independent reset operations:
  • The pin_perst0_n, pin_perst1_n input ports can trigger a cold reset. This clears sticky bits and resets the physical layer.
  • The pin_perst_n continues to affect the entire R-Tile. Toggling pin_perst_n affects both port 0 and port 1.
  • pX_warm_perst_n_i input ports can trigger a warm reset. This will not clear the sticky bits but will reset the physical layer.
    Input Port Used Sticky Bits Clearing Non-Sticky Bits Clearing PHY Lane Reset
    pin_perst_n Yes Yes Yes
    pin_perst0_n, pin_perst1_n Yes Yes Yes
    pX_warm_perst_n_i No Yes Yes
  • pin_perst_n has the highest priority for reset over pin_perst0_n, pin_perst1_n or pX_warm_perst_n_i ports.
  • When pin_perst_n is deasserted (i.e., high), the pin_perst0_n and pin_perst1_n input ports can be used to trigger a cold reset operation in each of the PCIe cores independently.
  • When pin_perst_n, pin_perst0_n and pin_perst1_n are deasserted (i.e., high), the pX_warm_perst_n_i input ports can be used to trigger a warm reset operation in each of the PCIe cores independently.
    Figure 6.  pX_warm_perst_n_i vs pin_perst_n/pin_perst0_n/pin_perst1_n behavior
  • Concurrent assertions of the reset input ports pin_perst_n, pin_perst0_n, pin_perst1_n and pX_warm_perst_n_i are not supported.
  • Usage of the pX_warm_perst_n_i to perform a warm reset to one of the active cores must happen only after the deassertion (i.e. high) of the corresponding pX_reset_status_n port. As an example, in Configuration Mode 2 (2x8), in order to trigger an independent warm reset operation on p0_warm_perst_n_i, the p0_reset_status_n must be deasserted (i.e. high).
  • As is the case with pin_perst_n, once pin_perst0_n or pin_perst1_n has been asserted (i.e. low), the assertion needs to be held for a minimum of 100ms.
  • As is the case with pin_perst_n, once pX_warm_perst_n_i has been asserted (i.e. low), the assertion needs to be held for a minimum of 100ms.
  • pX_warm_perst_n_i assertion should be avoided during a functional-level reset or before a functional-level reset is completed since this could impact the link training process. In case this occurs, assert the corresponding pin_perst0_n or pin_perst1_n to properly complete the link training process.
  • When the pX_warm_perst_n_i ports are routed to General Purpose I/Os (GPIOs), the Application logic must implement a debounce logic to prevent the switch bouncing and triggering unintentional assertions. The debounce logic consists of a counter that waits for the signal to stabilize before propagating it to the targeted port. In case these ports are not routed to GPIOs and are being used by internal fabric logic only, the debounce logic is not necessary.
    Figure 7.  pX_warm_perst_n_i Signal Before and After Debounce Logic