R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.1.1. Standards and Specifications Compliance

  • PCI Express Base Specification Revision 5.0, Version 1.0
  • Single Root I/O Virtualization and Sharing Specification, Revision 1.1
  • Address Translation Services, Revision 1.1
  • Virtual I/O Device (VIRTIO) Version 1.0
  • PHY Interface for PCI Express Specification, Version 5.1.1
    Note: This interface is accessible when the IP is in PIPE mode.