R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.6.2. Enabling the R-Tile Debug Toolkit

To enable the R-Tile Debug Toolkit in your design, enable the option Enable Debug Toolkit in the Top-Level Settings tab of the R-Tile Avalon Streaming Intel FPGA IP for PCI Express. When the Debug Toolkit is enabled via the Enable Debug Toolkit parameter, the Hard IP Reconfiguration Interface is automatically enabled.

Note: When the Debug Toolkit is enabled via the Enable Debug Toolkit parameter, the PHY Reconfiguration interface is automatically enabled. A 100MHz clock must be provided on the xcvr_reconfig_clk port for proper functionality of the Debug Toolkit.