R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.5. Performance and Resource Utilization

The following table shows the recommended FPGA fabric speed grades for all the configurations that the R-Tile Avalon® streaming IP core supports.

Table 6.   Intel Agilex® 7 Recommended FPGA Fabric Speed Grades for All Avalon Streaming Widths and Frequencies

Configuration

Application Clock Frequency (MHz)

Recommended FPGA Fabric Speed Grades

Note
Gen5 1x16 EP/RP/BP

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2  
Gen4 1x16 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2
Gen3 1x16 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  
Gen5 2x8 EP/RP/BP

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2  
Gen4 2x8 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2 3
Gen3 2x8 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  
Gen5 4x4 EP/RP/BP

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2  
Gen4 4x4 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  

400 MHz 2

425 MHz

450 MHz

475 MHz

500 MHz

-1, -2, -3 2 3
Gen3 4x4 EP/RP/BP

250 MHz

275 MHz

300 MHz

-1, -2, -3  

PIPE Direct

500 -1, -2  

The following table shows the typical resource utilization information for selected configurations.

The resource usage is based on the Avalon® streaming IP core top-level entity (intel_rtile_pcie_ast) that includes IP core soft logic implemented in the FPGA fabric.

Table 7.  Resource Utilization Information for the R-Tile Avalon® Streaming IP
Link Configuration Device Family ALMs M20Ks Dedicated Logic Registers
Gen5 x16 Intel Agilex® 7 11721 0 32819
Gen4 x16 Intel Agilex® 7 11617 0 28127
Gen3 x16 Intel Agilex® 7 11617 0 28127
16-channel PIPE Direct Intel Agilex® 7 2257 0 1836

For more details on the R-Tile Avalon® Streaming design example, refer to R-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide.

2 -3 devices only support an Application Clock frequency up to 400 MHz.
3 This topology is only available in the following OPNs: AGIx027R29AxxxxR2, AGIx027R29AxxxxR3, AGIx027R29BxxxxR3, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1. For additional details on OPN decoding, refer to the Available Options section of the Intel Agilex® 7 FPGAs and SoCs Device Overview.