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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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1.4. Resource Utilization
The following numbers were obtained by compiling the PHY IP core for Stratix® 10 devices using the Quartus® Prime Pro Edition 24.1. The numbers of ALMs and logic registers are rounded up to the nearest 100.
IP variation | ALMs | Registers | M20K Blocks |
---|---|---|---|
Stratix® 10 10GBASE-KR PHY IP core (with Auto-negotiation and Link training) | 3511 | 4599 | 9 |