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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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7.2.3. Design Example Interface Signals
The Stratix® 10 10GBASE-KR testbench is self-contained and does not require you to drive any input signals.
Signal | Direction | Description |
---|---|---|
pll_refclk | Input | Transceiver reference clock. Drive at 644.53125 or 322.255626 MHz. |
clk50 | Input | System clock input. Drive at 50 MHz. The intent is to drive this from a 50 MHz oscillator on the board. |
cpu_resetn | Input | Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core. |
user_pb[7:0] | Input | User push buttons. The hardware design example connects these bits to drive push buttons on the target board. |
ch0_rx_serial_data | Input | Channel 0 Transceiver PHY input serial data. |
ch1_rx_serial_data | Input | Channel 1 Transceiver PHY input serial data. |
ch0_tx_serial_data | Output | Channel 0 Transceiver PHY output serial data. |
ch1_tx_serial_data | Output | Channel 1 Transceiver PHY output serial data. |
user_led[7:0] | Output | Status signals. The hardware design example connects these bits to drive LEDs on the target board. |
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