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1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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2.5.4. Adding the Stratix® 10 Transceiver PHY Reset Controller
You must add an Stratix® 10 Transceiver PHY Reset Controller IP core to your design, and connect it to the Stratix® 10 10GBASE-KR PHY IP core reset signals. This block implements a reset sequence that resets the device transceiver correctly.
You can use the IP Catalog to create a transceiver PHY reset controller. In the Stratix® 10 Transceiver PHY Reset Controller IP parameter editor, you must perform the following for compatibility with the 10GBASE-KR PHY IP core:
- Select the RX digital reset mode to Manual if auto-negotiation mode is enabled.