Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458
Date 10/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 7 FPGAs and SoCs 2. Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs 18. Device Security for Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs 20. Power Management for Agilex™ 7 FPGAs and SoCs 21. Software and Tools for Agilex™ 7 FPGAs and SoCs 22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 7 FPGAs and SoCs 1.2. Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 7 SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Agilex™ 7 FPGAs and SoCs F-Series 2.2. Agilex™ 7 FPGAs and SoCs I-Series 2.3. Agilex™ 7 FPGAs and SoCs M-Series 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview

6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs

The Agilex™ 7 FPGAs and SoCs carry over the variable-precision DSP architecture from previous FPGAs with hard fixed point and IEEE 754-compliant floating point capabilities.

In fixed point mode, you can configure the DSP blocks to support signal processing with precisions from 9×9 up to 54×54:

  • Increased 9×9 multipliers count, with three 9×9 multipliers for every 18×19 multiplier
  • A pipeline register increases the maximum DSP block operating frequency and reduces the power consumption
  • Dynamically switch multiplier inputs through scanin and chainout signals
  • Compile each DSP block independently as four 9×9, two 18×19, or one 27×27 multiply-accumulate

The variable-precision DSP supports floating point addition, multiplication, multiply-add, and multiply-accumulate:

  • Single-precision 32-bit arithmetic FP32 floating point mode
  • Half-precision 16-bit arithmetic FP16 and FP19 floating point modes, and BFLOAT16 floating point format

With a dedicated 64-bit cascade bus, you can cascade multiple variable-precision DSP blocks to efficiently implement even higher-precision DSP functions.

Figure 7. Low Precision Fixed Point Mode
Figure 8. Standard Precision Fixed Point Mode
Figure 9. High Precision Fixed Point Mode
Figure 10. Half Precision 16-bit Arithmetic Floating PointThis block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Figure 11. Single Precision 32-bit Arithmetic Floating PointThis block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Table 21.  Variable-Precision DSP Block Configurations in Agilex™ 7 FPGAs and SoCs This table lists the way Agilex™ 7 FPGAs and SoCs accommodate the different precisions within a DSP block or by utilizing multiple DSP blocks.
Multiplier DSP Block Resource Usage Expected Application
9×9 bits

One-fourth of a variable-precision DSP block

(One DSP block can support four 9×9)

 Low-precision fixed point
18×19 bits Half of a variable-precision DSP block Medium-precision fixed point
27×27 bits One variable-precision DSP block High-precision fixed point
19×36 bits One variable-precision DSP block with external adder Fixed point fast Fourier transform (FFT)
36×36 bits Two variable-precision DSP blocks with external adder Very high-precision fixed point
54×54 bits Four variable-precision DSP blocks with external adder Double-precision fixed point
Half-precision floating point

One variable-precision DSP block

(Contains adder for two FP16 multipliers with one accumulator)

 Half-precision floating point
Single-precision floating point

One variable-precision DSP block

(Contains one FP32 multipliers with one accumulator)

 Single-precision floating point
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