Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458
Date 10/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 7 FPGAs and SoCs 2. Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs 18. Device Security for Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs 20. Power Management for Agilex™ 7 FPGAs and SoCs 21. Software and Tools for Agilex™ 7 FPGAs and SoCs 22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 7 FPGAs and SoCs 1.2. Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 7 SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Agilex™ 7 FPGAs and SoCs F-Series 2.2. Agilex™ 7 FPGAs and SoCs I-Series 2.3. Agilex™ 7 FPGAs and SoCs M-Series 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview

22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview

Document Version Changes
2024.10.09 Updated information about PCS features in E-Tile transceivers.
2024.04.01
  • Updated the ethernet MAC row in the table listing the features specific to Agilex 7 SoCs.
  • Added package 3184E with F-Tile ×2 and R-Tile ×2 (package code R31E) for the AGI 041 device.
  • Removed package 3695A.
  • Retitled "Available Options" to "Part Number Decoder".
  • Updated the figure showing the ordering part number:
    • Added package 3184E to I-Series FPGAs.
    • Removed package 3695A from M-Series FPGAs.
    • Added optional suffixes B and C.
  • Added links to updated lists of available Agilex™ 7 FPGAs and SoCs.
  • In the summary of Agilex™ 7 SoCs key features, updated the eMMC support from version 4.5 to 5.0.
2023.10.31
  • Added package 2340A with F-Tile ×1 (package code R24D) for AGF 006, AGF 008, AGF 012, and AGF 014 devices.
  • Added package 3184B to M-Series FPGAs.
  • Removed package 3695B from M-Series FPGAs.
2023.09.07 Removed Ethernet AVB from the list of Ethernet standards that the HPS supports.
2023.07.05 Corrected typographical error in the table summarizing the device family features.
2023.04.19
  • Added package 3184B to the AGI 041 device.
  • Removed packages 3184B and 3687A from M-Series FPGAs.
  • Added packages 3695A and 3695B to M-Series FPGAs.
2023.02.20 Added the AGI 041 device.
2023.01.10
  • Moved all D-Series information to new Intel® Agilex™ 5 FPGAs and SoCs Device Overview
  • Updated product family name to " Intel® Agilex™ 7 FPGAs and SoCs"
  • Updated the I-Series FPGA packages
    • Added CXL* column to package 1085A
    • Added package 3184A
  • Updated the figure showing the ordering part numbers
  • Updated the table that lists the tile types, hardened IPs, and applications
2022.09.26
  • Added the D-Series FPGAs and SoCs
  • Restructured and rewrote the document
2022.06.09
  • Updated the ordering part numbers
  • Removed the 3184A package
  • Added information about FHT and FGT transceivers
  • Added M-Series FPGAs with F-Tile and HBM2E package options
  • Updated the figure showing the hard memory controller
2022.04.06 Updated package code "R19A" to "R18A" in the ordering part number.
2022.03.06
  • Revised key innovations in Agilex™ 7 FPGAs and SoCs:
    • DDR5 supports up to 5600 Mbps per pin
    • Intel 7 technology in the M-Series
  • Added Agilex™ 7 SoC FPGAs M-Series
  • Added M-Series in the Agilex™ 7 Ordering Part Number (OPN) figure
  • Added block diagram for the M-Series in the Agilex™ 7 FPGA and SoC Block Diagram
  • Added support for the M-Series FPGAs and SoCs including the AGM 032 and AGM 039 devices
  • Added Heterogeneous 3D Stacked HBM2E DRAM Memory
2021.12.05
  • Updated Agilex™ 7 FPGA and SoC Device Overview
  • Globally revised key innovations in Agilex™ 7 FPGAs and SoCs:
    • Device densities of up to 4 million equivalent logic elements
    • Configurable networking support is up to 6 x 400G or 12 x 200G in a single device
    • Over 25K of 18x19 multipliers, or over 50K of 9x9 multipliers in a single device
    • Over 389 Mb of embedded RAM in the largest device
  • Updated description of the following features in the Feature Summary table:
    • Technology
    • General purpose I/Os
    • Core clock networks
    • Packaging
  • Globally added AGI 035 and AGI 040 devices support for the I-Series
2021.07.22 Added Adaptive Logic Modules (ALM) count in the Agilex™ 7 FPGAs and SoCs F-Series Family Plan and Agilex™ 7 FPGAs and SoCs I-Series Family Plan tables.
2021.06.21
  • Updated Agilex™ 7 FPGA and SoC Device Overview
  • Renamed 10nm FinFET process Technology to 10nm SuperFin Technology
  • Updated specification and package code in the Agilex™ 7 FPGAs and SoCs Ordering Part Number (OPN) figure
  • Added new high-performance crypto blocks feature
  • Globally added AGF 014 and AGF 022 devices support for the F-Series FPGAs
  • Globally added AGI 019 and AGI 023 devices support for the I-Series FPGAs
  • Added new topic: High-Performance Crypto Block
  • Revised figures and diagrams.
2021.04.19
Sections Updated:
  • Available Options
  • Agilex™ 7 FPGA and SoC Family Plan
2021.03.23
Sections Updated:
  • Agilex™ 7 SoC FPGAs M-Series
  • Available Options
  • Agilex™ 7 FPGA and SoC Summary of Features
  • Agilex™ 7 FPGA and SoC Family Plan
  • Heterogeneous 3D SiP Transceiver Tile
  • Agilex™ 7 FPGA Transceivers
  • External Memory and General Purpose I/O
2020.09.30
Sections Updated:
  • Agilex™ 7 FPGA and SoC Device Overview
  • Agilex™ 7 FPGA and SoC Summary of Features
  • Agilex™ 7 FPGA and SoC Family Plan
  • Hyperflex® Core Architecture
  • Agilex™ 7 FPGA Transceivers
2019.07.02
Sections Updated:
  • Agilex™ 7 FPGA and SoC Device Overview
  • Agilex™ 7 FPGA and SoC Family Variants
  • Agilex™ 7 SoC FPGAs F-Series
  • Agilex™ 7 SoC FPGAs I-Series
  • Agilex™ 7 SoC FPGAs M-Series
  • Common Features
  • Available Options
  • FPGA and SoC Summary of Features
  • FPGA and SoC Family Plan
  • Hyperflex® Core Architecture
  • Heterogeneous 3D SiP Transceiver Tile
  • PCS Features
  • P-Tile Transceivers
  • External Memory and General Purpose I/O
  • Adaptive Logic Module (ALM)
  • Internal Embedded Memory
  • Variable Precision DSP
  • Device Security
2019.04.02 Initial Release
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