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1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
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Ixiasoft
12.4. R-Tile Transceivers
The R-Tile transceivers are PCIe* transceivers with hardened CXL* IP.
Features of the R-Tile transceivers:
- Support up to PCIe* 5.0 ×16 at 32 Gbps
- Port bifurcation support—2×8 endpoint or 4×4 root port
- TL bypass features
- Configuration via protocol (CvP)
- Autonomous hard IP
- Separate header and payload interfaces on the user interface
- Single-root I/O virtualization (SR-IOV)—8 physical functions or 2K virtual functions
- VirtIO support
- Scalable IOV
- Shared Virtual Memory
- Precise time management
- PIPE direct
- Hardened CXL* IP, up to PCIe* 5.0 ×16 endpoint
- Selected features support CXL* 1.1 and 2.0 specifications
- Soft logic (encrypted) to support CXL* Type 1, Type 2, or Type 3 devices
- Mix and manage different memory types and controllers