Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/09/2024
Public
Document Table of Contents

12.4. R-Tile Transceivers

The R-Tile transceivers are PCIe* transceivers with hardened CXL* IP.

Features of the R-Tile transceivers:

  • Support up to PCIe* 5.0 ×16 at 32 Gbps
  • Port bifurcation support—2×8 endpoint or 4×4 root port
  • TL bypass features
  • Configuration via protocol (CvP)
  • Autonomous hard IP
  • Separate header and payload interfaces on the user interface
  • Single-root I/O virtualization (SR-IOV)—8 physical functions or 2K virtual functions
  • VirtIO support
  • Scalable IOV
  • Shared Virtual Memory
  • Precise time management
  • PIPE direct
  • Hardened CXL* IP, up to PCIe* 5.0 ×16 endpoint
  • Selected features support CXL* 1.1 and 2.0 specifications
  • Soft logic (encrypted) to support CXL* Type 1, Type 2, or Type 3 devices
  • Mix and manage different memory types and controllers