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1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
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7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
Agilex™ 7 FPGAs and SoCs use programmable clock tree synthesis for its core clocking function.
Programmable clock tree synthesis uses dedicated clock tree routing and switching circuits. These dedicated circuits enable the Quartus® Prime software to create the exact clock trees that your design requires.
Advantages of using programmable clock tree synthesis:
- Minimizes clock tree insertion delay
- Reduces dynamic power dissipation in the clock tree
- Allows greater flexibility of clocking in the core
- Maintains backwards compatibility with legacy global and regional clocking schemes
Features of the core clock network of Agilex™ 7 FPGAs and SoCs:
- Supports the second-generation Hyperflex® core architecture
- Supports the hard memory controllers33 for:
- DDR4—up to 3,200 Mbps with a quarter-rate transfer to the core
- DDR5—up to 5,600 Mbps
- LPDDR5—up to 5,500 Mbps
- Supported by dedicated clock input pins and integer I/O PLLs
33 Each Agilex™ 7 FPGA series has different hard memory controller support. For more information, refer to the related information.