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1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
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13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
Agilex™ 7 FPGAs and SoCs M-Series offer options for integrated HBM2E DRAM memory. The HBM2E memory blocks are inside the package together with the high-performance FPGA core fabric, transceiver tiles, and HPS.
The in-package inclusion of the HBM2E memory results in a near-memory compute implementation that allows up to 820 GBps total aggregate memory bandwidth. This aggregate bandwidth is an increase of over ten times compared to DDR5 memory bandwidth. A near-memory configuration also reduces system power by reducing traces between the FPGA and memory, while also reducing board area.
Some M-Series FPGAs have two integrated HBM2E DRAM memory stacks inside the package. Each DRAM stack contains:
- 8 GB or 16 GB density per stack with 16 GB or 32 GB total density per device
- 410 GBps memory bandwidth per stack with 820 GBps total aggregate memory bandwidth per device
- Eight 128-bits wide independent channels or sixteen 64-bits wide independent pseudo channels
- Data transfer rates of up to 3.2 Gbps per signal between the core fabric and the HBM2E DRAM memory
The core fabric of the M-Series FPGAs can interface with the HBM2E directly or through the hardened memory NoC.
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