Visible to Intel only — GUID: iid1670997381162
Ixiasoft
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
Visible to Intel only — GUID: iid1670997381162
Ixiasoft
10.1. External Memory Interface Performance
Interface Protocol | Memory Controller | Interface Performance (Mbps) | Maximum Width (Bits) |
---|---|---|---|
DDR4 | Hard | 3,200 | 64 / 72 |
QDRIV | Soft | 2,133 | 36 |
Interface Protocol | Memory Controller | Interface Performance (Mbps) | Maximum Width (Bits) | |
---|---|---|---|---|
DDR4 | Hard | 3,200 | Component | 40 |
DIMM | 72 | |||
DDR5 | Hard | 5,600 | Component | 40 |
DIMM | 2×40 | |||
LPDDR5 | Hard | 5,500 | 4×16 | |
QDRIV | Soft | 2,133 | 36 |