Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/09/2024
Public
Document Table of Contents

2.2. Agilex™ 7 FPGAs and SoCs I-Series

Table 8.  I-Series FPGA Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device Logic Element Adaptive Logic Module eSRAM M20K MLAB DSP Crypto Block
Count Size (Mb) Count Size (Mb) Count Size (Mb) Count 18x19 Multiplier
AGI 019 1,918,975 650,500 1 18 8,500 166 35,525 20 1,354 2,708 2
AGI 023 2,308,080 782,400 1 18 10,464 204 39,120 24 1,640 3,280 2
AGI 022 2,208,075 748,500 10,900 212 37,425 23 6,250 12,500
AGI 027 2,692,760 912,800 13,272 259 45,640 28 8,528 17,056
AGI 035 3,540,000 1,200,000 3 54 14,931 292 60,000 37 9,594 19,188 4
AGI 040 4,047,400 1,372,000 3 54 19,908 389 68,600 42 12,792 25,584 4
AGI 041 4,000,672

1,356,160

2 36

17,136

335 67,808 42 4
Note: Agilex™ 7 FPGAs and SoCs support PCIe* blocks in tile locations 15A, 14C, and 15C. CXL* is supported in tile locations 14C and 15C in the 2957A package only.
Table 9.  I-Series FPGA Family Plan—Transceivers and HPSThe values in this table are maximum resources or performance.
Device

CXL* Lane

F-Tile R-Tile

HPS

Transceiver Channel

Ethernet Block

12

PCIe* Controller

13

PCIe* 14/

CXL* 15 Controller

FGT 16

FHT 17

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGI 019 16

64

48

8

8 4 18 4 19 1 Yes
AGI 023 16

64

48

8

8 4 18 4 19 1 Yes
AGI 022 32

64

48

8

8 4 18 4 19 3 Yes
AGI 027 32

64

48

8

8 4 18 4 19 3 Yes
AGI 035

96

72

24

24 6 20 6 21
AGI 040

96

72

24

24 6 20 6 21
AGI 041 32 64 48 8 8 4 4 3 Yes
Table 10.  I-Series FPGA Packages with F-TileTable reading example: In package 3184B of AGI 022, there are 720 GPIOs, of which, 360 are LVDS. There are four F-Tiles with FGT channels supporting a maximum total of 64× 32 Gbps NRZ or 48× 58 Gbps PAM4, and FHT channels supporting a maximum total of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4.
Device Package

(Grid Array: Hexagonal)

3184B

(56 mm × 45 mm)

0.92 mm pitch

3948A

(56 mm × 56 mm)

0.92 mm pitch

GPIO LVDS F-Tile ×4 GPIO LVDS F-Tile ×6
FGT FHT FGT FHT

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGI 019 480 240 64 48 8 8
AGI 023 480 240 64 48 8 8
AGI 022 720 360 64 48 8 8
AGI 027 720 360 64 48 8 8
AGI 035 576 288 96 72 24 24
AGI 040 576 288 96 72 24 24
AGI 041 732 366 64 48 8 8
Table 11.  I-Series FPGA Packages with F-Tile and R-Tile—1805A and 2957ATable reading example: In package 2957A of AGI 022, there are 720 GPIOs, of which, 360 are LVDS. There is one F-Tile with FGT channels supporting a maximum of 16× 32 Gbps NRZ or 12× 58 Gbps PAM4, and FHT channels supporting a maximum of 4× 58 Gbps NRZ or 4× 116 Gbps PAM4. There are three R-Tiles supporting a maximum total of 48× PCIe* at up to 32 Gbps per lane, or 32× CXL* lanes.
Device Package

(Grid Array: Hexagonal)

1805A

(42.5 mm × 42.5 mm)

1.025 mm pitch

2957A

(56 mm × 45 mm)

1.0 or 0.92 mm pitch

GPIO LVDS F-Tile ×1 R-Tile ×1 GPIO LVDS F-Tile ×1 R-Tile ×3
FGT

32 Gbps

PCIe*

CXL*

FGT FHT

32 Gbps

PCIe*

CXL*

22

32 Gbps

NRZ

58 Gbps

PAM4

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGI 019 480 240 16 12 16 16
AGI 023 480 240 16 12 16 16
AGI 022 720 360 16 12 4 4 48 32
AGI 027 720 360 16 12 4 4 48 32
AGI 041 720 360 16 12 4 4 48 32
Table 12.  I-Series FPGA Packages with F-Tile and R-Tile—3184A and 3184ETable reading example: In package 3184A of AGI 022, there are 720 GPIOs, of which, 360 are LVDS. There are three F-Tiles with FGT channels supporting a maximum total of 48× 32 Gbps NRZ or 36× 58 Gbps PAM4, and FHT channels supporting a maximum of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. There is one R-Tile supporting a maximum of 16× PCIe* at up to 32 Gbps per lane, or 16× CXL* lanes.
Device Package

(Grid Array: Hexagonal)

3184A

(56 mm × 45 mm)

0.92 mm pitch

3184E

(56 mm × 45 mm)

0.92 mm pitch

GPIO LVDS F-Tile ×3 R-Tile ×1 GPIO LVDS F-Tile ×2 R-Tile ×2
FGT FHT

32 Gbps

PCIe*

CXL* FGT FHT

32 Gbps

PCIe*

CXL*

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGI 022 720 360 48 36 8 8 16 16
AGI 027 720 360 48 36 8 8 16 16
AGI 041 744 372 32 24 8 8 32 32
12 Maximum 10, 25, 40, 50, 100, 200, or 400 GbE MAC and FEC hard IP blocks.
13 Maximum PCIe* hard IP blocks ( PCIe* 4.0 ×16) or bifurcatable two PCIe* 4.0 ×8 (EP) or four PCIe* 4.0 ×4 (RP).
14 Maximum PCIe* hard IP blocks ( PCIe* 5.0 ×16) or bifurcatable two PCIe* 5.0 ×8 (EP) or four PCIe* 5.0 ×4 (RP).
15 Maximum CXL* hard IP blocks ( PCIe* 5.0 ×16) endpoint.
16 Maximum F-Tile general purpose transceiver (FGT) RS and KP FEC NRZ up to 32 Gbps, or PAM4 up to 58 Gbps.
17 Maximum F-Tile high speed transceiver (FHT) RS and KP FEC NRZ up to 58 Gbps, or PAM4 up to 116 Gbps.
18 Maximum of four F-Tiles in package 3184B.
19 Maximum of four PCIe* controllers in package 3184B.
20 Maximum of six F-Tiles in package 3948A.
21 Maximum of six PCIe* controllers in package 3948A.
22 For options to increase available CXL* lanes, contact Intel Premier Support and quote ID #15012021851.