Visible to Intel only — GUID: hcw1551901783774
Ixiasoft
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
Visible to Intel only — GUID: hcw1551901783774
Ixiasoft
12.1.1. PMA Features in E-Tile Transceivers
The transmitter, receiver, and high speed clocking resources form the PMA channels. The transmit features deliver exceptional signal integrity at data rates up to 58 Gbps PAM4 or 28.9 Gbps NRZ. Additionally, each PMA features advanced equalization circuits that compensate for transmission losses across a wide frequency spectrum.
Feature | Capability |
---|---|
Data rates | Up to 58 Gbps |
Optical module support | XFP, QSFP-DD, OSFP, QSFP/QSFP28, QSFP56, SFP+, SFP28, SFP56, CFP/CFP2/CFP4 optical modules support |
Cable driving support | SFP+ Direct Attach, eSATA |
Transmit pre-emphasis |
|
Dynamic reconfiguration | Allows for independent control of each transceiver channel Avalon memory-mapped interface for the most transceiver flexibility |
Multiple PCS–PMA and PCS–Core to FPGA fabric interface widths |
16, 20, 32, 40, or 64 bits interface width for flexible deserialization width, encoding, and reduced latency |