Agilex™ 7 FPGAs and SoCs Device Overview

Download PDF
ID 683458
Date 10/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 7 FPGAs and SoCs 2. Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs 18. Device Security for Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs 20. Power Management for Agilex™ 7 FPGAs and SoCs 21. Software and Tools for Agilex™ 7 FPGAs and SoCs 22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 7 FPGAs and SoCs 1.2. Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 7 SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Agilex™ 7 FPGAs and SoCs F-Series 2.2. Agilex™ 7 FPGAs and SoCs I-Series 2.3. Agilex™ 7 FPGAs and SoCs M-Series 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview

1.5.1. Intel® Agilex™ F-Series SoC FPGAs

Table 3.   Intel® Agilex™ F-Series FPGAs and SoCs Family Plan Part-1
Intel® Agilex™ F-Series Device Names Logic Elements (LE) Adaptive Logic Modules (ALM) eSRAM Blocks eSRAM Mbits M20K Blocks M20K Mbits MLAB Counts MLAB Mbits Variable Precision DSP Blocks 18x19 Multipliers
AGF 006 573,480 194,400 0 0 2,844 56 9,720 6 1,640 3,280
AGF 008 764,640 259,200 0 0 3,792 74 12,960 8 2,296 4,592
AGF 012 1,178,525 399,500 2 36 5,900 115 19,975 12 3,743 7,486
AGF 014 1,437,240 487,200 2 36 7,110 139 24,360 15 4,510 9,020
AGF 019 1,918,975 650,500 1 18 8,500 166 35,525 20 1,354 2,708
AGF 023 2,308,080 782,400 1 18 10,464 204 39,120 24 1,640 3,280
AGF 022 2,208,075 748,500 0 0 10,900 212 37,425 23 6,250 12,500
AGF 027 2,692,760 912,800 0 0 13,272 259 45,640 28 8,528 17,056
Table 4.   Intel® Agilex™ F-Series FPGAs and SoCs Family Plan Part-2
Intel® Agilex™ F-Series Device Names Crypto Blocks

F-Tile

FGT Transceiver Channels

1

F-Tile Ethernet Blocks

2

F-Tile

PCIe Controllers

3

P-Tile

PCIe Controllers

4

E-Tile

Ethernet Blocks

5

E-Tile

Transceiver Channels

6

HPS Option
AGF 006 0

24x PAM4/

32x NRZ

 2 2 0 0 0 Yes
AGF 008 0

24x PAM4/

32x NRZ

 2 2 0 0 0 Yes
AGF 012 0

24x PAM4/

32x NRZ

 2 2 1 4

8x PAM4/

16x NRZ

 Yes
AGF 014 0

24x PAM4/

32x NRZ

 2 2 1 4

8x PAM4/

16x NRZ

 Yes
AGF 019 2

48x PAM4/

64x NRZ

 4 4 2 4

12x PAM4/

24x NRZ

 Yes
AGF 023 2

48x PAM4/

64x NRZ

 4 4 2 4

12x PAM4/

24x NRZ

 Yes
AGF 022 0

48x PAM4/

64x NRZ

 4 4 2 4

12x PAM4/

24x NRZ

 Yes
AGF 027 0

48x PAM4/

64x NRZ

 4 4 2 4

12x PAM4/

24x NRZ

 Yes
Table 5.   Intel® Agilex™ F-Series FPGAs with F-Tile Package Options and I/O Pins

Key: GPIO (LVDS) / F-Tile 32G (58G).

Example: If an entry in the table below contains 384(192)/32(24), it means 384 GPIO of which 192 are LVDS; thirty-two 32G NRZ channels or twenty-four 58G PAM4 channels.

Intel® Agilex™ F-Series Device Names 1546A 7 2340A 8 3184C 9
AGF 006 384(192)/32(24) 576(288)/32(24) —
AGF 008 384(192)/32(24) 576(288)/32(24) —
AGF 012 — 744(372)/32(24) —
AGF 014 — 744(372)/32(24) —
AGF 019 — 480(240)/32(24) 480(240)/64(48)
AGF 023 — 480(240)/32(24) 480(240)/64(48)
AGF 022 — 744(372)/32(24) 720(360)/64(48)
AGF 027 — 744(372)/32(24) 720(360)/64(48)
Table 6.   Intel® Agilex™ F-Series FPGAs with P-Tile and E-Tile Package Options and I/O Pins

Key: GPIO (LVDS) / E-Tile 28.9G (58G) / P-Tile 16G PCIe.

Example: If an entry in the table below contains 768(384)/16(8)/16, it means that 768 GPIO of which 384 are LVDS; sixteen 28.9 NRZ channels or eight 58G PAM4 channels; and sixteen up to 16G/lane PCIe.

Intel® Agilex™ F-Series Device Names 2486A 10 2581A 11
AGF 006 — —
AGF 008 — —
AGF 012 768(384)/16(8)/16 —
AGF 014 768(384)/16(8)/16 —
AGF 019 — 480(240)/24(12)/32
AGF 023 — 480(240)/24(12)/32
AGF 022 — 624(312)/24(12)/32
AGF 027 — 624(312)/24(12)/32
1 Maximum F-Tile Transceiver Channels PAM4 (up to 58 Gbps) - RS & KP FEC NRZ (up to 32 Gbps)
2 Maximum F-Tile 10/25/40/50/100/200/400G Ethernet MAC + FEC hard IP blocks
3 Maximum F-Tile PCIe hard IP blocks (Gen4 x 16) or Bifurcateable 2x PCIe Gen4 x8 (EP) or 4x Gen4 x4 (RP)
4 Maximum P-Tile PCIe hard IP blocks (Gen4x16 ) or Bifurcateable 2x PCIe Gen4 x8 (EP) or 4x Gen4 x4 (RP)
5 Maximum E-Tile 100G Ethernet MAC + FEC hard IP Blocks
6 Maximum E-Tile Transceiver Channels PAM4 (up to 58 Gbps) - RS & KP FEC NRZ (up to 28.9 Gbps)
7 (F-Tile x2) (Dimension: 37.5 mm x 34 mm, Pitch (mm): 0.92 Hex )
8 (F-Tile x2) (Dimension: 45 mm x 42 mm, Pitch (mm): 0.92 Hex)
9 (F-Tile x4) (Dimension: 56 mm x 45 mm, Pitch (mm): 0.92 Hex)
10 (E-Tile + P-Tile) (Dimension: 55 mm x 42.5 mm, Pitch (mm): 1.0 Hex)
11 (E-Tile + P-Tile x2) (Dimension: 52.5 mm x 40.5 mm, Pitch (mm): 0.94/0.92 Hex)
Level Two Title