Agilex™ 7 SoC FPGA Boot User Guide

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ID 683389
Date 8/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Agilex™ 7 SoC FPGA Boot Flow 8. SoC FPGA Boot User Guide Archives 9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide A. Boot Scratch Registers
1. Introduction x
1.1. Glossary 1.2. Agilex™ 7 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration - First Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.2. Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. Golden System Reference Design and Design Examples x
5.1. Golden System Reference Design 5.2. Bootloader Examples 5.3. Additional Design Examples
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux 6.3. FPGA Partial Reconfiguration from Linux
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition 7.3. Other Debug Considerations
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
A. Boot Scratch Registers x
A.1. BOOT_SCRATCH_COLD0 A.2. BOOT_SCRATCH_COLD1 A.3. BOOT_SCRATCH_COLD2 A.4. BOOT_SCRATCH_COLD3 A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5 A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7 A.7. BOOT_SCRATCH_COLD8 A.8. BOOT_SCRATCH_COLD9 A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers

4.10. Partial Reconfiguration

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically, while the rest of the FPGA design continues to function. The portion that can be reconfigured is referred to as PR region while the FPGA design that is to be configured in the PR region is referred to as PR persona. All areas not occupied by PR regions in your project is referred to as static region. You can associate the static region with the top-level partition of the design. The static region contains both the core and periphery locations of the device. The static region bitstream configures this region.

You can define multiple PR personas for a particular region in your design (for example: PR persona0, PR persona1, etc.), without impacting operation in areas outside the region. This methodology is effective in systems with multiple functions that time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems.

When PR is used, the FPGA hardware design needs to be built enabling PR support. For this, the following components are needed as part of the static FPGA region:
  • PR Freeze Bridge—Before performing the PR, all the interfaces between the PR region and the rest of the FPGA must be isolated (frozen). This module is used for this purpose. Depending on the design in the PR, more than one bridge may be needed.
  • PR Freeze Controller—This handles the freezing mechanism. Before PR is performed, this module freezes all the PR bridges and after PR is done, this unfreezes the interfaces and takes the PR region out of reset.

In use cases where partial reconfiguration is controlled by the HPS, the PR process is initiated by the HPS software sending the PR bitstream (persona .rbf file) to the SDM. This can be done from Linux using the device tree overlay mechanism described in the FPGA Partial Reconfiguration from Linux section.

The following figure describes an example of the PR concept. This also shows the associated IPs added to the FPGA design and how these are connected to the HPS.

Figure 32. Example of the PR Concept

The process to create the RBF file is shown in the following figure and for this, the Quartus® Prime Software is used. This flow extends from the standard configuration flow to generate the .pmsf files for each one of the persona PR designs which are then converted in to the corresponding personaX.rbf file. The PR design for each persona are included as part of the hardware project. The FPGA design to be loaded into the static region is built as part of the standard build flow.

The command used to create the RBF files is shown next: 
# Command to create personaX.rbf
quartus_pfg -c personaX.pmsf personaX.rbf
Figure 33. Process to Create the RBF File
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