Agilex™ 7 SoC FPGA Boot User Guide

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ID 683389
Date 8/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Agilex™ 7 SoC FPGA Boot Flow 8. SoC FPGA Boot User Guide Archives 9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide A. Boot Scratch Registers
1. Introduction x
1.1. Glossary 1.2. Agilex™ 7 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration - First Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.2. Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. Golden System Reference Design and Design Examples x
5.1. Golden System Reference Design 5.2. Bootloader Examples 5.3. Additional Design Examples
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux 6.3. FPGA Partial Reconfiguration from Linux
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition 7.3. Other Debug Considerations
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
A. Boot Scratch Registers x
A.1. BOOT_SCRATCH_COLD0 A.2. BOOT_SCRATCH_COLD1 A.3. BOOT_SCRATCH_COLD2 A.4. BOOT_SCRATCH_COLD3 A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5 A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7 A.7. BOOT_SCRATCH_COLD8 A.8. BOOT_SCRATCH_COLD9 A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers

6.3. FPGA Partial Reconfiguration from Linux

The Partial Reconfiguration started from Linux relies on the device tree overlay mechanism which allows you to modify the original device tree at run time.

The components needed to perform the Platform Reconfiguration from Linux are listed next. These items are already provided as part of the Partial Reconfiguration example provided in the following RocketBoards page: Agilex™ 7 SoC GSRD: Partial Reconfiguration

  • dtbt—This is a script used to manage the overlay. This script provides the dtbt command that can be called from the Linux shell providing the ability to add or remove an overlay to the device tree and also list the overlays currently applied. This is located under Linux file system at /sbin directory. The source code for this script can be seen from the altera-opensource / dtbt web page.
  • pr_fpga_static_region.dtbo—This is the overlay for the static region. This is generated from the pr_fpga_static_region.dts file and creates the new device tree nodes that describe the PR region and the freeze controller. The attributes for the PR region node are expected to be updated by the PR persona overlays. This overlay needs to be applied before persona overlays. This file is located under Linux file system at the /boot/devicetree directory. Next is shown the structure of the static region device tree overlay DTS.
    Note: The static region and PR region can also be defined directly from the initial Linux device tree as alternative to use an overlay for this purpose. 
    fragment@0 {
    target-path = "/soc/base_fpga_region";  /* Device tree hierarchy */
    :
    __overlay__ {
        external-fpga-config;
          :
	   /* PR region node */
          fpga_pr_regionN{
            compatible = "fpga-region";
            fpga-bridges = <&freeze_controller_0>;
            :
           };   
           /* PR freeze Controller node */
           freeze_controller@offset {
             compatible = "altr,freeze_controller-ver", "altr,freeze-bridge-controller";
             :
           };
      };
};
  • pr_personaX.dtbo—This is the overlay for the PR Persona X and extends the fpga_pr_regionN node created in the PR Static Region overlay. This overlay is generated from the pr_personaX.dts file. Here is where it is indicated which is the RBF file that corresponds to the FPGA design to be loaded in the PR region (referred to as the personaX.rbf). This overlay also defines additional nodes and specific attributes that applies for this persona in the PR region node in the device tree. There is a PR Persona overlay file for each persona FPGA design to be loaded in the PR region. These overlay files are located under Linux file system at the /boot/devicetree directory. Next is shown the structure of the PR Persona Overlay DTS.
    fragment@1 {
    target-path = "/soc/base_fpga_region/fpga_pr_regionN";
     :
    __overlay__ {
       partial-fpga-config;
       firmware-name = "personaX.rbf";  /* RBF file for this persona */
       :
       /* Specific attributes for this PR Persona in fpga_pr_regionN  node*/
       :
       pr_region_N_nodeA:{
            /* Specific attributes for this PR Persona in sub node A */

       };
       pr_region_N_nodeB:{
            /* Specific attributes for this PR Persona in sub node B */

       };
    };
};

  • personaX.rbf—This is the bitstream used by personaX overlay and corresponds to the FPGA design to be loaded into the PR region.

    During the partial reconfiguration started by Linux, this accesses the PR RBF files under its file system at the /lib/firmware directory.
    Note: In the hardware design, it is not allowed enabling both SGMII and PR at the same time. Because of this, the hardware design needs to be recompiled with SGMII disabled and PR enabled to allow PR to be used.
The following figure shows the components involved in Partial Reconfiguration for 2 Persona using the Linux device tree overlays mechanism:
Figure 34. Components Involved
As indicated before, to perform the partial reconfiguration from Linux, we make use of the dtbt command which allows the device tree overlays handling. At the time that the overlay is applied, the PR is performed automatically, and the Linux driver associated to the overlay is loaded. The following table lists some of the functionality that this command provides:
Description Command Usage
List overlays applied dtbt -l
Add an overlay dtbt -a <.dtbo to apply> -p <.dtbo search path>
Remove an overlay dtbt -r <.dtbo to remove > -p <.dtbo search path>
Note: When the PR overlay is removed, the corresponding Linux driver is removed.
To perform the PR successfully, the following sequence should be followed from the Linux shell:
  1. Load static region overlay and confirm that this was applied by listing the overlays. 
    # dtbt -a pr_fpga_static_region.dtbo -p /boot/devicetree
# dtbt -l

    Only one static region overlay should be shown.

  2. Perform PR by loading the desired overlay and confirm that this was applied by listing the overlays applied.
    # dtbt -a pr_persona0.dtbo -p /boot/devicetree
# dtbt -l

    Static region and persona0 overlays should be shown.

  3. If another PR persona wants to be loaded, the current PR persona overlay needs to be removed and then the new PR Persona overlay should be applied.
    root@agilex:~# dtbt -r pr_persona0.dtbo -p /boot/devicetree
root@agilex:~# dtbt -a pr_persona1.dtbo -p /boot/devicetree
root@agilex:~# dtbt -l

    Static region and persona1 overlays should be shown.

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