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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
A.1. BOOT_SCRATCH_COLD0
A.2. BOOT_SCRATCH_COLD1
A.3. BOOT_SCRATCH_COLD2
A.4. BOOT_SCRATCH_COLD3
A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5
A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7
A.7. BOOT_SCRATCH_COLD8
A.8. BOOT_SCRATCH_COLD9
A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
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4.5.2. HPS Boots First
In order to configure a device over JTAG with HPS first, you need to generate a bitstream intended for AVST. Two RBF files are created: design.hps.rbf Phase 1 bitstream which is used for initial device configuration over JTAG, and design.core.rbf Phase 2 bitstream used for later fabric configuration by HPS software.
The following figure shows an overview of the process:
Figure 13. Configuration over JTAG with HPS Boots First
The following steps are involved:
- Compile hardware project with Quartus® Prime to obtain the SOF file.
- Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled one.
- Use Programming File Generator to create the following files:
- Peripheral RBF file—contains the phase 1 configuration bitstream for initial configuration over JTAG.
- Core RBF file—contains the phase 2 configuration bitstream. To be used by HPS software later to configure the fabric.
- Use Quartus® Prime Programmer to configure the device using the phase 1 peripheral RBF. HPS software starts running, beginning with HPS FSBL.
- At a later time, HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.
The following example creates the files for HPS boot first:
quartus_pfg -c design.sof design.rbf -o hps_path=fsbl.hex -o hps=on
The input and output files for this command are:
- Input Files:
- design.sof
- fsbl.hex
- Output Files:
- design.hps.rbf—Phase 1 Peripheral RBF
- design.core.rbf—Phase 2 Core RBF