Agilex™ 7 SoC FPGA Boot User Guide

ID 683389
Date 8/28/2024
Public
Document Table of Contents

9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide

Document Version Quartus® Prime Version Changes
2024.08.28 22.4 Made the following change:
2024.08.23 22.4 Made the following change:
2024.02.01 22.4 Made the following change:
  • Added the Boot Scratch Register appendix.
2024.01.17 22.4 Updated the Configuration over JTAG with HPS Boots First figure in the HPS Boots First section.
2023.09.08 22.4 Made the following change:
  • Updated information about "JTAG Configuration with HPS First" in HPS Boot First.
2023.06.29 22.4 Made the following changes:
  • Updated the list of "Output Files" in the HPS Boots First chapter.
  • Removed mentions of "SoC EDS" from the following chapters:
    • External Configuration Host Only
    • Single SDM Flash
2023.05.30 22.4 Made the following changes:
  • Updated product family name to " Agilex™ 7"
  • Updated Configuring the FPGA Fabric from U-Boot by adding the bridge disable command before the fpga load command.
2023.01.19 22.4 Made the following changes:
  • Added description of the REBOOT_HPS in the Reset section.
  • Added information about the maximum size of the .core.rbf and bit-stream in the Programming File Generator section.
  • Added a note to the Configuration over AVST section.
  • Added information about Partial Reconfiguration
  • Updated information in Configuration over JTAG section.
  • Added the Agilex™ 7 SoC FPGA Boot User Guide Archives section
  • Made changes to Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
    • Added the Quartus® Prime Version column
    • Converted this section from an appendix to a chapter
2021.11.10 21.4 Replaced the Supported QSPI Devices table with a link to the Intel® Supported Configuration Devices web page.
2021.05.28 21.1 Initial release