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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
A.1. BOOT_SCRATCH_COLD0
A.2. BOOT_SCRATCH_COLD1
A.3. BOOT_SCRATCH_COLD2
A.4. BOOT_SCRATCH_COLD3
A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5
A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7
A.7. BOOT_SCRATCH_COLD8
A.8. BOOT_SCRATCH_COLD9
A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
Visible to Intel only — GUID: xlg1510942221348
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9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
Document Version | Quartus® Prime Version | Changes |
---|---|---|
2024.08.28 | 22.4 | Made the following change:
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2024.08.23 | 22.4 | Made the following change:
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2024.02.01 | 22.4 | Made the following change:
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2024.01.17 | 22.4 | Updated the Configuration over JTAG with HPS Boots First figure in the HPS Boots First section. |
2023.09.08 | 22.4 | Made the following change:
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2023.06.29 | 22.4 | Made the following changes:
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2023.05.30 | 22.4 | Made the following changes:
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2023.01.19 | 22.4 | Made the following changes:
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2021.11.10 | 21.4 | Replaced the Supported QSPI Devices table with a link to the Intel® Supported Configuration Devices web page. |
2021.05.28 | 21.1 | Initial release |