Agilex™ 7 SoC FPGA Boot User Guide

ID 683389
Date 8/28/2024
Public
Document Table of Contents

3.1.2. Secure Device Manager

After the Agilex™ 7 SoC FPGA exits POR, the SDM samples the MSEL[2:0] pins to determine the boot source. Next, the device configures the SDM I/Os according to the selected boot source interface and the SDM retrieves the configuration bitstream through the interface.

The typical configuration bitstream for HPS boot first mode contains:
  • SDM configuration firmware
  • HPS external memory interface (EMIF) I/O configuration data
  • HPS FSBL code and HPS FSBL hardware handoff binary

The SDM completes the configuration of the HPS EMIF I/O and then copies the HPS FSBL to the HPS on-chip RAM.