Agilex™ 7 SoC FPGA Boot User Guide

Download PDF
ID 683389
Date 8/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Agilex™ 7 SoC FPGA Boot Flow 8. SoC FPGA Boot User Guide Archives 9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide A. Boot Scratch Registers
1. Introduction x
1.1. Glossary 1.2. Agilex™ 7 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration - First Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.2. Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. Golden System Reference Design and Design Examples x
5.1. Golden System Reference Design 5.2. Bootloader Examples 5.3. Additional Design Examples
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux 6.3. FPGA Partial Reconfiguration from Linux
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition 7.3. Other Debug Considerations
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
A. Boot Scratch Registers x
A.1. BOOT_SCRATCH_COLD0 A.2. BOOT_SCRATCH_COLD1 A.3. BOOT_SCRATCH_COLD2 A.4. BOOT_SCRATCH_COLD3 A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5 A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7 A.7. BOOT_SCRATCH_COLD8 A.8. BOOT_SCRATCH_COLD9 A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers

4.8.2. Creating Configuration Files Using Graphical Interface

The following example creates the CvP configuration files using the Programming File Generator in GUI mode:

  1. Start the Programming File Generator in GUI mode by running the qpfgw command.
  2. Select the Device Family to be Agilex™ 7.
  3. Select the Configuration mode to be Active Serial x4.
  4. In the Output Files tab:
    1. Change the output file Name to “design”.
    2. Check Raw Binary File for CvP Core Configuration (.rbf) option – the others are grayed out.
    3. Check the JTAG Indirect Configuration File for Periphery Configuration (.jic) sub-option
    4. Check the Memory Map File (.map) sub-option
    5. Optionally check the Raw Programming Data (.rpd) sub-option.
    6. Click the Raw Programming Data (.rpd) sub-option
    The Quartus® Prime Programming File Generator window is displayed:
    Figure 29.  Quartus® Prime Programming File Generator Pro Edition Window: Output Files
  5. Switch to Input Files tab by clicking it. In the Input Files tab, do the following:
    1. Click the Add Bitstream button, browse to your SOF file, then click Open.
    2. Click the newly added design.sof file, then click Properties. In the HPS settings > Bootloader section, click the “..” browse button, go to the location of your HPS FSBL hex file, select it and click Open.
    The Quartus® Prime Programming File Generator window is displayed:
    Figure 30.  Quartus® Prime Programming File Generator Pro Edition Window: Input Files
  6. Switch to the Configuration Device tab by clicking it. In the Configuration Device tab, do the following:
    1. Click Add device, select your desired flash device (in this example MT25QU128) then click OK
    2. Click the newly added device, then click Add Partition. In the partition window, leave Name as “P1”, select Input file to be “Bitstream_1 (design.sof)” and leave Page as “0”, Address Mode as “Auto”, then click OK.
    3. Under Flash Loader, click the Select.. button, then select Agilex™ 7 under Device Family, and AGFB014R24AR0 under Device Name. Click OK.
    The Quartus® Prime Programming File Generator window is displayed:
    Figure 31.  Quartus® Prime Programming File Generator Pro Edition Window: Configuration Device
  7. Click the Generate button. Once the files are generated, a confirmation message is received.
  8. Optionally, go to File > Save or File > Save As to save the configuration in a .pfg file. You can generate the output again by applying the same options by running the command line version of the tool like this: “quartus_pfg -c <filename.pfg>”.
Level Two Title