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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
A.1. BOOT_SCRATCH_COLD0
A.2. BOOT_SCRATCH_COLD1
A.3. BOOT_SCRATCH_COLD2
A.4. BOOT_SCRATCH_COLD3
A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5
A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7
A.7. BOOT_SCRATCH_COLD8
A.8. BOOT_SCRATCH_COLD9
A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
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4.2.2. Platform Designer Options
The HPS component instantiated in Platform Designer has various selectable HPS settings. You can access them by doing the following:
- Open the hardware project in the Quartus® Prime GUI.
- In the Quartus® Prime GUI, to Tools > Platform Designer to open the Platform Designer.
- When asked by Platform Designer, select and open the file instantiating the HPS component.
- In Platform Designer, click the HPS component and access the Parameters panel.
The available settings are grouped as follows:
- FPGA Interfaces
- General
- Bridges
- DMA Requests
- Interrupts
- HPS Clocks and Resets
- Input Clocks
- Internal Clocks and Output Clocks
- Resets
- IO Delays
- Pin Mux and Peripherals
For more information about these settings, refer to the Agilex™ 7 HPS Component User Guide.
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