Agilex™ 7 SoC FPGA Boot User Guide

ID 683389
Date 8/28/2024
Public
Document Table of Contents

2.1.2. Secure Device Manager

Once the Agilex™ 7 SoC FPGA exits POR, the SDM samples the MSEL[2:0] pins to determine the boot source. Next, the device configures the SDM I/Os according to the selected boot source interface and the SDM retrieves the configuration bitstream through the interface.

The typical configuration bitstream for FPGA configuration first contains:
  1. Configuration firmware for the SDM
  2. FPGA I/O and HPS external memory interface (EMIF) I/O configuration data
  3. FPGA core configuration data
  4. HPS FSBL code and FSBL hardware handoff binary data

The SDM completes the configuration of the FPGA core and I/O, and then copies the HPS FSBL code and HPS FSBL hardware handoff binary to the HPS on-chip RAM.