Visible to Intel only — GUID: oka1620321249466
Ixiasoft
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
A.1. BOOT_SCRATCH_COLD0
A.2. BOOT_SCRATCH_COLD1
A.3. BOOT_SCRATCH_COLD2
A.4. BOOT_SCRATCH_COLD3
A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5
A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7
A.7. BOOT_SCRATCH_COLD8
A.8. BOOT_SCRATCH_COLD9
A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
Visible to Intel only — GUID: oka1620321249466
Ixiasoft
4.7.2.1. Creating Configuration Files from Command Line
The following example creates the RBF file for HPS boot first:
quartus_pfg -c design.sof design.rbf -o hps_path=fsbl.hex -o hps=on
The input and output files for this command are:
- Input Files:
- design.sof
- fsbl.hex
- Output Files:
- design.hps.rbf
- design.core.rbf
The command parameter is listed below:
Parameter | Description |
---|---|
hps_path | Location of HPS FSBL file in hex format |
hps | Set to "on" to enable HPS boot first mode, omit for FPGA configuration first mode |