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1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
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Ixiasoft
3.4.1. Testbench
The generated example testbench is dynamic and has the same configuration as the IP. The testbench generates an external transceiver ATX PLL for both duplex and simplex directions.
Note: The Stratix® 10 example testbench includes the external transceiver PLL; the IP core does not include the transceiver PLL for these devices.
Figure 28. Serial Lite III Streaming Example Testbench (Duplex) for Stratix® 10 H-tile and L-tile Advanced Clocking Mode
Figure 29. Serial Lite III Streaming Example Testbench (Simplex) for Stratix® 10 H-tile and L-tile Advanced Clocking Mode