Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 5/23/2024
Public
Document Table of Contents

3.4.1. Testbench

The generated example testbench is dynamic and has the same configuration as the IP. The testbench generates an external transceiver ATX PLL for both duplex and simplex directions.

Note: The Stratix® 10 example testbench includes the external transceiver PLL; the IP core does not include the transceiver PLL for these devices.
Figure 28. Serial Lite III Streaming Example Testbench (Duplex) for Stratix® 10 H-tile and L-tile Advanced Clocking Mode
Figure 29. Serial Lite III Streaming Example Testbench (Simplex) for Stratix® 10 H-tile and L-tile Advanced Clocking Mode