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1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
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2.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the example designs in a Linux system:
- Quartus® Prime software
- ModelSim* , QuestaSim* , Riviera-PRO* , Xcelium* , or VCS* / VCS* MX simulator
- Stratix® 10 GX Signal Integrity Development Kit (1SG280HU1F50E2VG) for hardware testing
Note: To use the Stratix® 10 TX Signal Integrity development kit with H-tile design examples, you must generate the design examples without the development kit and remap the pins to match the Stratix® 10 TX Signal Integrity development kit.