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1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
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1.1. Directory Structure
The Quartus® Prime software generates the design example files in the following folders:
- <user_defined_design_example_directory>/ed_sim
- <user_defined_design_example_directory>/ed_synth
- <user_defined_design_example_directory>/ed_hwtest
The following diagrams show the directories that contain the generated files for the design examples.
Figure 2. Directory Structure for Stratix® 10 Serial Lite III Streaming Design Example
Directory/File | Description |
---|---|
ed_sim/tb_components | The folder that contains the testbench files. |
ed_sim/common | The folder that contains the .tcl scripts for all the simulators. |
ed_sim/cadence ed_sim/aldec ed_sim/mentor ed_sim/xcelium ed_sim/synopsys/vcs or ed_sim/synopsys/vcsmx |
The folder that contains the simulation script. It also serves as a working area for the simulator. |
ed_sim/altera_sl3_dup |
The folder that contains the design example simulation source files. |
ed_synth/seriallite_iii_streaming_demo.qpf | Quartus project file. |
ed_synth/seriallite_iii_streaming_demo.qsf | Quartus settings file. |
ed_synth/seriallite_iii_streaming_demo.sdc | Synopsys Design Constraints (SDC) file. |
ed_synth/src | The folder that contains the design example synthesizable components. |
ed_synth/src/seriallite_iii_streaming_demo.v | Design example top-level HDL. |
ed_synth/altera_sl3_dup/synth/altera_sl3_dup.v |
Design example DUT top-level files. |
ed_synth/demo_control |
The folder for each synthesizable component including Platform Designer generated IPs, such as demo_mgmt and demo_control. |
ed_hwtest | The folder that contains the design example hardware setup files. |
ed_hwtest/Readme.txt | Instruction file to download the generated design example on the development kit. |
ed_hwtest/master_export.v | User interface Verilog design file. This file is available when you instantiate a design with Synthesis enabled. |
ed_hwtest/master_export_hw.tcl | Component description file for master export custom IP. This file is available when you instantiate a design with Synthesis enabled. |
ed_hwtest/software | The folder that contains scripts to download the demo_control program into Nios® V processor and open an interactive terminal to run the design example. |