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1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel® FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Text Box Intel® FPGA IP
43. Tone Mapping Operator Intel® FPGA IP
44. Test Pattern Generator Intel® FPGA IP
45. Unsharp Mask Intel® FPGA IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer Intel® FPGA IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO Intel® FPGA IP
51. Video Timing Generator Intel® FPGA IP
52. Vignette Correction Intel® FPGA IP
53. Warp Intel® FPGA IP
54. White Balance Correction Intel® FPGA IP
55. White Balance Statistics Intel® FPGA IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
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42.3. Text Box IP Functional Description
The Text Box IP allows you to generate an output of a string of text. You can update the contents of the text box, if you turn on Memory-mapped control interface, otherwise it is a static text box with contents taken from the file provided in the Text file name parameter.
The number of characters per line and number of lines are fixed at compile-time. However if Memory-mapped control interface is on you can update the font size, font, and background colors and interlace configuration at run time. The field size changes as font size changes, and the field height halves if Fixed interlace nibble is 8 to 15..
Figure 116. Example Text Box
| Color Space | Number of color planes | Number of color planes with Enable alpha channel |
|---|---|---|
| RGB | 3 | 4 |
| YCbCr 4:4:4 | 3 | 4 |
| YCbCr 4:2:2 | 2 | 3 |
| YCbCr 4:20 | 3 | 4 |
| Monochrome | 1 | 2 |
Text Box Format
The number of characters per line is: n chars , and number of lines named is n lines . Character index is i.
The IP sequentially indexes each character starting from 0, with maximum index of:
(n chars x n lines )-1
that is:
0≤i ≤(n chars *n lines )-1}
The line or row number is:
i/n chars
The column number is:
i mod n chars
That is, the text wraps to the next line at index n chars .
If Memory-mapped control interface is on, you can write a string by writing the character's ASCII code to the corresponding addresses. The control interface takes 4 bytes of data, where characters are ordered in little-endian (to write the string "0123" (ASCII values 0x30, 0x31, 0x32, 0x33) you write "0x33323130" to address 0x200). You may use the control interface's byte-enable signal to write to specific bytes only.
If Memory-mapped control interface is off, the IP shows static text with the contents of the file in the Text file name parameter. The file automatically is formatted into an initialization file and used as ROM.
Field Dimensions
You select progressive or interlaced outputs with Fixed interlace nibble or in the FIELD_INTERLACE register.
The IP derives the field size from the font size, number of characters per line, and number of lines. Each character is 8x8 pixels with font size of 1. For progressive output:
- The width is (8 x font size x n_ chars )
- The height is (8 x font size x n_ lines )
For interlaced output, the IP halves the field height so that when deinterlacing F0 with F1 the output is identical to a progressive frame.
- The width is (8 x font size x n_ chars )
- The height is (4 x font size x n_ lines )
If Memory-mapped control interface is on, the field size updates whenever the font size or interlace settings change.