Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel® FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Text Box Intel® FPGA IP 43. Tone Mapping Operator Intel® FPGA IP 44. Test Pattern Generator Intel® FPGA IP 45. Unsharp Mask Intel® FPGA IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer Intel® FPGA IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO Intel® FPGA IP 51. Video Timing Generator Intel® FPGA IP 52. Vignette Correction Intel® FPGA IP 53. Warp Intel® FPGA IP 54. White Balance Correction Intel® FPGA IP 55. White Balance Statistics Intel® FPGA IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. Adaptive Noise Reduction Intel® FPGA IP x
10.1. About the Adaptive Noise Reduction IP 10.2. Adaptive Noise Reduction IP Parameters 10.3. Adaptive Noise Reduction IP Functional Description 10.4. Adaptive Noise Reduction IP Registers 10.5. Adaptive Noise Reduction IP Software API
10.1. About the Adaptive Noise Reduction IP x
10.1.1. Adaptive Noise Reduction IP Performance and Resources
10.3. Adaptive Noise Reduction IP Functional Description x
10.3.1. Adaptive Noise Reduction IP Interfaces
11. Advanced Test Pattern Generator Intel® FPGA IP x
11.1. About the Advanced Test Pattern Generator IP 11.2. Advanced Test Pattern Generator IP Parameters 11.3. Advanced Test Pattern Generator IP Functional Description 11.4. Advanced Test Pattern Generator IP Registers 11.5. Advanced Test Pattern Generator IP Software API
11.1. About the Advanced Test Pattern Generator IP x
11.1.1. Advanced Test Pattern Generator IP Performance and Resources
11.3. Advanced Test Pattern Generator IP Functional Description x
11.3.1. Test Patterns 11.3.2. Dimensions, Offsets, and Alpha Settings 11.3.3. Run-time Settings 11.3.4. Advanced Test Pattern Generator IP Interfaces
12. AXI-Stream Broadcaster Intel® FPGA IP x
12.1. About the AXI-Stream Broadcaster IP 12.2. AXI-Stream Broadcaster IP Parameters 12.3. AXI-Stream Broadcaster IP Interfaces
12.1. About the AXI-Stream Broadcaster IP x
12.1.1. AXI-Stream Broadcaster IP Features 12.1.2. AXI-Stream Broadcaster IP Performance and Resources
13. Bits per Color Sample Adapter Intel® FPGA IP x
13.1. About the Bits per Color Sample Adapter IP 13.2. Bits per Color Sample Adapter IP Parameters 13.3. Bits per Color Sample Adapter IP Dithering Functional Description 13.4. Bits per Color Sample Adapter IP Registers 13.5. Bits per Color Sample Adapter Software API
13.1. About the Bits per Color Sample Adapter IP x
13.1.1. Bits per Color Sample Adapter IP Performance and Resources
13.3. Bits per Color Sample Adapter IP Dithering Functional Description x
13.3.1. Bits per Color Sample Adapter IP Interfaces
14. Black Level Correction Intel® FPGA IP x
14.1. About the Black Level Correction IP 14.2. Black Level Correction IP Parameters 14.3. Black Level Correction IP Functional Description 14.4. Black Level Correction IP Registers 14.5. Black Level Correction IP Software API
14.1. About the Black Level Correction IP x
14.1.1. Black Level Correction IP Performance and Resources
14.3. Black Level Correction IP Functional Description x
14.3.1. Black Level Correction IP Interfaces
15. Black Level Statistics Intel® FPGA IP x
15.1. About the Black Level Statistics IP 15.2. Black Level Statistics IP Parameters 15.3. Black Level Statistics IP Interfaces 15.4. Black Level Statistics IP Registers 15.5. Black Level Statistics IP Software API
15.1. About the Black Level Statistics IP x
15.1.1. Black Level Statistics IP Performance and Resources
16. Chroma Key Intel® FPGA IP x
16.1. About the Chroma Key IP 16.2. Chroma Key IP Parameters 16.3. Chroma Key IP Interfaces 16.4. Chroma Key Replacement 16.5. Chroma Key IP Registers 16.6. Chroma Key IP Software API
16.1. About the Chroma Key IP x
16.1.1. Chroma Key IP Performance and Resources
17. Chroma Resampler Intel® FPGA IP x
17.1. About the Chroma Resampler IP 17.2. Chroma Resampler IP Parameters 17.3. Chroma Resampler IP Functional Description 17.4. Chroma Resampler IP Registers 17.5. Chroma Resampler IP Software API
17.1. About the Chroma Resampler IP x
17.1.1. Chroma Resampler Performance and Resources
17.3. Chroma Resampler IP Functional Description x
17.3.1. Chroma Resampler IP Interfaces
18. Clipper Intel® FPGA IP x
18.1. About the Clipper IP 18.2. Clipper IP Parameters 18.3. Clipper IP Interfaces 18.4. Clipper IP Registers 18.5. Clipper IP Software API
18.1. About the Clipper IP x
18.1.1. Clipper IP Performance and Resources
19. Clocked Video Input Intel® FPGA IP x
19.1. About the Clocked Video Input IP 19.2. Initializing the Clocked Video Input IP 19.3. Clocked Video Input IP Parameters 19.4. Clocked Video Input IP Interfaces 19.5. Clocked Video Input IP Registers 19.6. Clocked Video Input IP Software API
19.1. About the Clocked Video Input IP x
19.1.1. Clocked Video Input IP Features 19.1.2. Clocked Video Input IP Performance and Resources
20. Clocked Video to Full-Raster Converter Intel® FPGA IP x
20.1. About the Clocked Video to Full-Raster Converter IP 20.2. Clocked Video to Full-Raster Converter Parameters 20.3. Clocked Video to Full-Raster Converter Block Description 20.4. Clocked Video Converter to Full-Raster IP Registers
20.1. About the Clocked Video to Full-Raster Converter IP x
20.1.1. Clocked Video to Full-Raster Converter Features 20.1.2. Clocked Video to Full-Raster Converter Performance and Resources
20.3. Clocked Video to Full-Raster Converter Block Description x
20.3.1. Clocked Video to Full-Raster Converter Interfaces
21. Clocked Video Output Intel® FPGA IP x
21.1. About the Clocked Video Output IP 21.2. Clocked Video Output IP Parameters 21.3. Clocked Video Output IP Functional Description 21.4. Clocked Video Output IP Interfaces 21.5. Clocked Video Output IP Registers 21.6. Clocked Video Output IP Software API
21.1. About the Clocked Video Output IP x
21.1.1. Clocked Video Output IP Performance and Resources 21.1.2. Clocked Video Output IP Features
22. Color Plane Manager Intel® FPGA IP x
22.1. About the Color Plane Manager IP 22.2. Color Plane Manager IP Parameters 22.3. Color Plane Manager IP Functional Description 22.4. Color Plane Manager IP Registers 22.5. Color Plane Manager Software API
22.1. About the Color Plane Manager IP x
22.1.1. Color Plane Manager IP Performance and Resources
22.3. Color Plane Manager IP Functional Description x
22.3.1. Color Plane Manager IP Interfaces
23. Color Space Converter Intel® FPGA IP x
23.1. About the Color Space Converter IP 23.2. Color Space Converter IP Parameters 23.3. Color Space Converter IP Functional Description 23.4. Color Space Converter IP Registers 23.5. Color Space Converter IP Software API
23.1. About the Color Space Converter IP x
23.1.1. Color Space Converter IP Features 23.1.2. Color Space Converter IP Performance and Resources
23.3. Color Space Converter IP Functional Description x
23.3.1. Color Space Converter IP Interfaces
24. Defective Pixel Correction Intel® FPGA IP x
24.1. About the Defective Pixel Correction IP 24.2. Defective Pixel Correction IP Parameters 24.3. Defective Pixel Correction IP Functional Description 24.4. Defective Pixel Correction IP Registers 24.5. Defective Pixel Correction IP Software API
24.1. About the Defective Pixel Correction IP x
24.1.1. Defective Pixel Correction IP Performance and Resources
24.3. Defective Pixel Correction IP Functional Description x
24.3.1. Defective Pixel Correction IP Interfaces
25. Deinterlacer Intel® FPGA IP x
25.1. About the Deinterlacer IP 25.2. Deinterlacer Parameters 25.3. Deinterlacer IP Functional Description 25.4. Deinterlacer IP Registers 25.5. Deinterlacer IP Software API
25.1. About the Deinterlacer IP x
25.1.1. Deinterlacer Performance and Resources
25.3. Deinterlacer IP Functional Description x
25.3.1. Deinterlacer Interfaces
26. Demosaic Intel® FPGA IP x
26.1. About the Demosaic IP 26.2. Demosaic IP Parameters 26.3. Demosaic IP Functional Description 26.4. Demosaic IP Registers 26.5. Demosaic IP Software API
26.1. About the Demosaic IP x
26.1.1. Demosaic IP Performance and Resources
26.3. Demosaic IP Functional Description x
26.3.1. Demosaic IP Interfaces
27. FIR Filter Intel® FPGA IP x
27.1. About the FIR Filter 27.2. FIR Filter Parameters 27.3. FIR Filter IP Operation 27.4. FIR Filter Interfaces 27.5. FIR Filter Registers 27.6. FIR Filter IP Software API
27.1. About the FIR Filter x
27.1.1. FIR Filter IP Performance and Resources
27.3. FIR Filter IP Operation x
27.3.1. FIR Filter Processing 27.3.2. FIR Filter Precision 27.3.3. FIR Coefficient Specification 27.3.4. FIR Filter Symmetry 27.3.5. Result to Output Data Type Conversion
27.3.4. FIR Filter Symmetry x
27.3.4.1. No Symmetry 27.3.4.2. Horizontal Symmetry 27.3.4.3. Vertical Symmetry 27.3.4.4. Horizontal and Vertical Symmetry 27.3.4.5. Diagonal Symmetry
28. Frame Cleaner Intel® FPGA IP x
28.1. About the Frame Cleaner IP 28.2. Frame Cleaner IP Parameters 28.3. Frame Cleaner IP Functional Description 28.4. Frame Cleaner IP Interfaces 28.5. Frame Cleaner IP Registers 28.6. Frame Cleaner IP Software API
28.1. About the Frame Cleaner IP x
28.1.1. Frame Cleaner IP Performance and Resources
29. Full-Raster to Clocked Video Converter Intel® FPGA IP x
29.1. About the Full-Raster to Clocked Video Converter 29.2. Full Raster to Clocked Video Converter Parameters 29.3. Full-Raster to Clocked Video Converter Block Description 29.4. Full-Raster to Clocked Video Converter Registers
29.1. About the Full-Raster to Clocked Video Converter x
29.1.1. Full-Raster to Clocked Video Converter Features 29.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
29.3. Full-Raster to Clocked Video Converter Block Description x
29.3.1. Full Raster to Clocked Video Converter Interfaces
30. Full-Raster to Streaming Converter Intel® FPGA IP x
30.1. About the Full-Raster to Streaming Converter IP 30.2. Full-Raster to Streaming Converter Parameters 30.3. Full-Raster to Streaming Converter Block Description
30.1. About the Full-Raster to Streaming Converter IP x
30.1.1. Full-Raster to Streaming Converter Features 30.1.2. Full-Raster to Streaming Converter Performance and Resources
30.3. Full-Raster to Streaming Converter Block Description x
30.3.1. Full-Raster to Streaming Converter Interfaces
31. Genlock Controller Intel® FPGA IP x
31.1. About the Genlock Controller IP 31.2. Genlock Controller IP Parameters 31.3. Genlock Controller IP Functional Description 31.4. Using Genlock Controller IP Software 31.5. Genlock Controller IP Registers 31.6. Genlock Controller IP Software API
31.1. About the Genlock Controller IP x
31.1.1. Genlock Controller IP Performance and Resources
31.3. Genlock Controller IP Functional Description x
31.3.1. Genlock Controller IP Interfaces
31.4. Using Genlock Controller IP Software x
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 31.4.3. Setting the VCXO hold over 31.4.4. Restarting the Genlock Controller IP 31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 31.4.7. Disturbing a Reference Clock (a cable pull)
32. Generic Crosspoint Intel® FPGA IP x
32.1. About the Generic Crosspoint IP 32.2. Generic Crosspoint IP Parameters 32.3. Generic Crosspoint IP Interfaces 32.4. Generic Crosspoint IP Registers 32.5. Generic Crosspoint IP Software API
32.1. About the Generic Crosspoint IP x
32.1.1. Generic Crosspoint IP Features 32.1.2. Generic Crosspoint Performance and Resources
33. Genlock Signal Router Intel® FPGA IP x
33.1. About the Genlock Signal Router IP 33.2. Genlock Signal Router IP Parameters 33.3. Genlock Signal Router IP Interfaces 33.4. Genlock Signal Router IP Registers 33.5. Genlock Signal Router IP Software API
33.1. About the Genlock Signal Router IP x
33.1.1. Genlock Signal Router IP Features 33.1.2. Genlock Signal Router IP Performance and Resources
34. Guard Bands Intel® FPGA IP x
34.1. About the Guard Bands IP 34.2. Guard Bands IP Parameters 34.3. Guard Bands IP Interfaces 34.4. Guard Bands IP Registers 34.5. Guard Bands IP Software API
34.1. About the Guard Bands IP x
34.1.1. Guard Bands IP Performance and Resources
35. Histogram Statistics Intel® FPGA IP x
35.1. About the Histogram Statistics IP 35.2. Histogram Statistics IP Parameters 35.3. Histogram Statistics IP Interfaces 35.4. Histogram Statistics IP Registers 35.5. Histogram Statistics IP Software API
35.1. About the Histogram Statistics IP x
35.1.1. Histogram Statistics IP Performance and Resources
36. Interlacer Intel® FPGA IP x
36.1. About the Interlacer IP 36.2. Interlacer IP Parameters 36.3. Interlacer IP Functional Description 36.4. Interlacer IP Registers 36.5. Interlacer IP Software API
36.1. About the Interlacer IP x
36.1.1. Interlacer IP Performance and Resources
36.3. Interlacer IP Functional Description x
36.3.1. Interlacer IP Interfaces
37. Mixer Intel® FPGA IP x
37.1. About the Mixer IP 37.2. Mixer IP Parameters 37.3. Mixer IP Functional Description 37.4. Mixer IP Registers 37.5. Mixer IP Software API
37.1. About the Mixer IP x
37.1.1. Mixer IP Performance and Resources
37.3. Mixer IP Functional Description x
37.3.1. Mixer IP Interfaces
38. Pixels in Parallel Converter Intel® FPGA IP x
38.1. About the Pixels in Parallel Converter IP 38.2. Pixels in Parallel Converter IP Parameters 38.3. Pixels in Parallel Converter Interfaces 38.4. Pixels in Parallel Converter Registers 38.5. Pixels in Parallel Converter IP Software API
38.1. About the Pixels in Parallel Converter IP x
38.1.1. Pixels in Parallel Converter IP Performance and Resources
39. Scaler Intel® FPGA IP x
39.1. About the Scaler 39.2. Scaler IP Parameters 39.3. Scaler IP Functional Description 39.4. Scaler IP Registers 39.5. Scaler IP Software API
39.1. About the Scaler x
39.1.1. Scaler IP Performance and Resources
39.2. Scaler IP Parameters x
39.2.1. Scaler Maximum Resolution
39.3. Scaler IP Functional Description x
39.3.1. Coefficient Selection 39.3.2. Coefficient Quantization 39.3.3. Filter Behavior at Edge Boundaries 39.3.4. Partial Frame Scaling 39.3.5. 422 and 420 Chroma Sampled Data Scaling 39.3.6. Scaler IP Interfaces
39.3.1. Coefficient Selection x
39.3.1.1. Updating Scaler IP Runtime Coefficients
40. Stream Cleaner Intel® FPGA IP x
40.1. About the Stream Cleaner IP 40.2. Stream Cleaner IP Parameters 40.3. Stream Cleaner IP Functional Description
40.1. About the Stream Cleaner IP x
40.1.1. Stream Cleaner IP Performance and Resources
40.3. Stream Cleaner IP Functional Description x
40.3.1. Stream Cleaner IP Interfaces
41. Switch Intel® FPGA IP x
41.1. About the Switch IP 41.2. Switch IP Parameters 41.3. Switch IP Functional Description 41.4. Switch IP Registers 41.5. Switch IP Software API
41.1. About the Switch IP x
41.1.1. Switch IP Performance and Resources
41.3. Switch IP Functional Description x
41.3.1. Switch IP Latency 41.3.2. Switch IP Interfaces
42. Text Box Intel® FPGA IP x
42.1. About the Text Box IP 42.2. Text Box IP Parameters 42.3. Text Box IP Functional Description 42.4. Text Box IP Registers 42.5. Text Box IP Software API
42.1. About the Text Box IP x
42.1.1. Text Box IP Performance and Resources
42.3. Text Box IP Functional Description x
42.3.1. Writing Text at Run Time with Double Buffering 42.3.2. Writing Text at Run Time without Double Buffering 42.3.3. Text Box IP Interfaces
43. Tone Mapping Operator Intel® FPGA IP x
43.1. About the Tone Mapping Operator IP 43.2. TMO IP Parameters 43.3. TMO IP Block Description 43.4. TMO IP Registers 43.5. TMO IP Software API
43.1. About the Tone Mapping Operator IP x
43.1.1. TMO IP Features 43.1.2. TMO IP Performance and Resource Utilization
43.3. TMO IP Block Description x
43.3.1. TMO IP Interfaces 43.3.2. TMO IP Latency
44. Test Pattern Generator Intel® FPGA IP x
44.1. About the Test Pattern Generator IP 44.2. Test Pattern Generator IP Parameters 44.3. Test Pattern Generator IP Functional Description 44.4. Test Pattern Generator IP Registers 44.5. Test Pattern Generator IP Software API
44.1. About the Test Pattern Generator IP x
44.1.1. Test Pattern Generator IP Performance and Resources
44.3. Test Pattern Generator IP Functional Description x
44.3.1. Test Patterns 44.3.2. Output Subsampling and Color Space 44.3.3. Run-time Settings 44.3.4. Test Pattern Generator IP Interfaces
45. Unsharp Mask Intel® FPGA IP x
45.1. About the Unsharp Mask IP 45.2. Unsharp Mask IP Parameters 45.3. Unsharp Mask IP Functional Description 45.4. Unsharp Mask IP Registers 45.5. Unsharp Mask IP Software API
45.1. About the Unsharp Mask IP x
45.1.1. Unsharp Mask IP Performance and Resources
45.3. Unsharp Mask IP Functional Description x
45.3.1. Unsharp Mask IP Interfaces
46. Video and Vision Monitor Intel FPGA IP x
46.1. About the Video and Vision Monitor IP 46.2. Video and Vision Monitor IP Parameters 46.3. Video and Vision Monitor IP Functional Description 46.4. Video and Vision Monitor IP Registers 46.5. Video and Vision Monitor Software API
46.1. About the Video and Vision Monitor IP x
46.1.1. Video and Vision Monitor IP Performance and Resources
46.3. Video and Vision Monitor IP Functional Description x
46.3.1. Video and Vision Monitor IP Interfaces
47. Video Frame Buffer Intel® FPGA IP x
47.1. About the Video Frame Buffer IP 47.2. Video Frame Buffer IP Parameters 47.3. Video Frame Buffer IP Functional Description 47.4. Video Frame Buffer IP Registers 47.5. Video Frame Buffer IP Software API
47.1. About the Video Frame Buffer IP x
47.1.1. Video Frame Buffer Performance and Resources
47.3. Video Frame Buffer IP Functional Description x
47.3.1. Video Frame Buffer IP Interfaces
48. Video Frame Reader Intel FPGA IP x
48.1. About the Video Frame Reader IP 48.2. Video Frame Reader IP Parameters 48.3. Video Frame Reader IP Functional Description 48.4. Video Frame Reader IP Registers 48.5. Video Frame Reader IP Software API
48.1. About the Video Frame Reader IP x
48.1.1. Video Frame Reader IP Performance and Resources
48.3. Video Frame Reader IP Functional Description x
48.3.1. Video Frame Reader IP Interfaces
49. Video Frame Writer Intel FPGA IP x
49.1. About the Video Buffer Writer IP 49.2. Video Frame Writer IP Parameters 49.3. Video Frame Writer IP Functional Description 49.4. Video Frame Writer IP Registers 49.5. Video Frame Writer IP Software API
49.1. About the Video Buffer Writer IP x
49.1.1. Video Frame Writer IP Performance and Resources
49.3. Video Frame Writer IP Functional Description x
49.3.1. Video Frame Writer IP Interfaces
50. Video Streaming FIFO Intel® FPGA IP x
50.1. About the Video Streaming FIFO IP 50.2. Video Streaming FIFO IP Parameters 50.3. Video Streaming FIFO IP Interfaces
50.1. About the Video Streaming FIFO IP x
50.1.1. Video Streaming FIFO IP Performance and Resources
51. Video Timing Generator Intel® FPGA IP x
51.1. About the Video Timing Generator IP 51.2. Video Timing Generator IP Parameters 51.3. Video Timing Generator IP Functional Description 51.4. Video Timing Generator IP Interfaces 51.5. Video Timing Generator IP Registers 51.6. Video Timing Generator IP Software API
51.1. About the Video Timing Generator IP x
51.1.1. Video Timing Generator IP Features 51.1.2. Video Timing Generator IP Performance and Resources
52. Vignette Correction Intel® FPGA IP x
52.1. About the Vignette Correction IP 52.2. Vignette Correction IP Parameters 52.3. Vignette Correction IP Interfaces 52.4. Vignette Correction IP Registers 52.5. Vignette Correction IP Software API
52.1. About the Vignette Correction IP x
52.1.1. Vignette Correction IP Performance and Resources
53. Warp Intel® FPGA IP x
53.1. About the Warp IP 53.2. Warp IP Parameters 53.3. Warp IP Block Description 53.4. Warp IP Registers 53.5. Warp IP Software API
53.1. About the Warp IP x
53.1.1. Warp IP Features 53.1.2. Warp IP Performance and Resource Utilization
53.3. Warp IP Block Description x
53.3.1. Block Cache Tool 53.3.2. Warp IP Interfaces 53.3.3. Warp IP Latency 53.3.4. External Memory for Warp IP
53.5. Warp IP Software API x
53.5.1. Using Warp IP Software 53.5.2. Warp IP Software Code Examples
54. White Balance Correction Intel® FPGA IP x
54.1. About the White Balance Correction IP 54.2. White Balance Correction IP Parameters 54.3. White Balance Correction IP Functional Description 54.4. White Balance Correction IP Registers 54.5. White Balance Correction IP Software API
54.1. About the White Balance Correction IP x
54.1.1. White Balance Correction IP Performance and Resources
54.3. White Balance Correction IP Functional Description x
54.3.1. White Balance Correction IP Interfaces
55. White Balance Statistics Intel® FPGA IP x
55.1. About the White Balance Statistics IP 55.2. White Balance Statistics IP Parameters 55.3. White Balance Statistics IP Interfaces 55.4. White Balance Statistics IP Registers 55.5. White Balance Statistics IP Software API
55.1. About the White Balance Statistics IP x
55.1.1. White Balance Statistics IP Performance and Resources
56. Design Security x
56.1. Memory Subsystems 56.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel® FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Text Box Intel® FPGA IP
43. Tone Mapping Operator Intel® FPGA IP
44. Test Pattern Generator Intel® FPGA IP
45. Unsharp Mask Intel® FPGA IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer Intel® FPGA IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO Intel® FPGA IP
51. Video Timing Generator Intel® FPGA IP
52. Vignette Correction Intel® FPGA IP
53. Warp Intel® FPGA IP
54. White Balance Correction Intel® FPGA IP
55. White Balance Statistics Intel® FPGA IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide

11.5. Advanced Test Pattern Generator IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios V HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

Register definition file: intel_vvp_adv_tpg_regs.h

Include file: intel_vvp_adv_tpg.h

Table 115.  Advanced Test Pattern Generator IP Software API
Name Description
intel_vvp_adv_tpg_init Initialize the Advanced Test Pattern Generator instance
intel_vvp_core_*

Accessors defined in Video and Vision Processing IPs

Software Programming Model. Writable when Lite is on.

Readable when Lite is off and Debug features is on.

intel_vvp_adv_tpg_get_lite_mode Returns if Lite mode is on
intel_vvp_adv_tpg_get_debug_enabled Returns if Debug enabled is on
intel_vvp_adv_tpg_get_bits_per_sample Returns the number of bits per color sample
intel_vvp_adv_tpg_get_pixels_in_parallel Returns the number of pixels processed in parallel per clock cycle
intel_vvp_adv_tpg_get_color_space Returns the color space and subsampling used across all patterns
intel_vvp_adv_tpg_get_pattern_type Returns the output pattern type of a given pattern number
intel_vvp_adv_tpg_get_num_patterns Returns the number of patterns enabled
intel_vvp_adv_tpg_commit_writes Commits all outstanding writes excluding pattern configuration registers
intel_vvp_adv_tpg_get_status Returns the contents of the status register
intel_vvp_adv_tpg_is_running Returns whether the IP is currently generating video data
intel_vvp_adv_tpg_get_commit_status Returns true if the IP has any outstanding writes, excluding writes to pattern configuration registers
intel_vvp_adv_tpg_get_fields_since_last_start Returns the number of fields the IP generates since it was last started
intel_vvp_adv_tpg_enable Start/stop the IP
intel_vvp_adv_tpg_is_enabled Returns whether the IP is currently enabled
intel_vvp_adv_tpg_start Stop the IP; alias for intel_vvp_adv_tpg_enable
intel_vvp_adv_tpg_stop Start the IP; alias for intel_vvp_adv_tpg_enable
intel_vvp_adv_tpg_get_field_width Returns the width of outgoing video fields.
intel_vvp_adv_tpg_set_field_width Set the width of outgoing video fields
intel_vvp_adv_tpg_get_field_height Returns the height of outgoing video fields.
intel_vvp_adv_tpg_set_field_height Set the height of outgoing video fields
intel_vvp_adv_tpg_get_field_interlace Returns the current interlace configuration/nibble
intel_vvp_adv_tpg_set_field_interlace Set the interlace configuration/nibble of outgoing video fields
intel_vvp_adv_tpg_get_pattern_width Returns the configured width of test patterns
intel_vvp_adv_tpg_set_pattern_width Set the width of test patterns
intel_vvp_adv_tpg_get_pattern_height Returns the configured height of test patterns
intel_vvp_adv_tpg_set_pattern_height Sets the height of test patterns
intel_vvp_adv_tpg_get_pattern_alpha Returns the opaqueness of test patterns
intel_vvp_adv_tpg_set_pattern_alpha Set the opaqueness of test patterns
intel_vvp_adv_tpg_get_pattern_horiz_offset Returns the configured horizontal offset of test patterns
intel_vvp_adv_tpg_set_pattern_horiz_offset Sets the horizontal offset from the left of test patterns
intel_vvp_adv_tpg_get_pattern_vert_offset Return the configured vertical offset of test patterns
intel_vvp_adv_tpg_set_pattern_vert_offset Set the vertical offset from the left of test patterns
Table 116.  Advanced Test Pattern Generator IP Software API

These API functions do not need a call to intel_vvp_adv_tpg_commit_writes to take effect; writing to the PATTERN_X_SELECT register is selfcontained.

Name Description
intel_vvp_adv_tpg_set_bars_type Select a type of color bars for the bars pattern
intel_vvp_adv_tpg_set_constant_colors Select the color for the constant color pattern
intel_vvp_adv_tpg_set_zone_plate_settings Sets the zone plate settings
intel_vvp_adv_tpg_set_zone_plate_settings_s Sets the zone plate settings using a helper structure
intel_vvp_adv_tpg_set_digital_clock_settings Sets the digital clock settings
intel_vvp_adv_tpg_set_digital_clock_settings_s Sets the digital clock settings using a helper structure

enum eIntelAdvTpgPatternType

Members

kIntelVvpAdvTpgBarsPattern - Bars pattern

kIntelVvpAdvTpgConstantColorPattern - Uniform pattern

kIntelVvpAdvTpgPathologicalPattern - Pattern that stresses SDI receiving equipment

kIntelVvpAdvTpgZonePlatePattern - Zone plate pattern

kIntelVvpAdvTpgDigitalClockPattern - Digital clock pattern

kIntelVvpAdvTpgInvalidPattern - Invalid pattern (indicates errors)

Description

Enumeration for the supported pattern types

enum eIntelAdvTpgColorSpace

Members

kIntelVvpAdvTpgRgb - RGB 4:4:4

kIntelVvpAdvTpgYcc444 - YcbCr/YUV 4:4:4

kIntelVvpAdvTpgYcc422 - YcbCr/YUV 4:2:2

kIntelVvpAdvTpgYcc420 - YcbCr/YUV 4:2:0

kIntelVvpAdvTpgMono - Monochrome

kIntelVvpAdvTpgInvalidColor - Invalid color space/subsampling (indicates errors)

Description

Enumeration for the supported color spaces and subsampling

enum eIntelAdvTpgBarsType

Members

Members kIntelVvpAdvTpgColorBars - Standard color bars

kIntelVvpAdvTpgGreyBars - Grey bars

kIntelVvpAdvTpgBlackWhiteBars - Alternating black and white bars

kIntelVvpAdvTpgMixedBars - Mixed type bars

kIntelVvpAdvTpgInvalidBars - Invalid bars pattern (indicates errors)

Description

Enumeration for the supported color bar patterns

struct intel_vvp_adv_tpg_zone_plate_settings

Members

uint16_t origin_x - The desired zone plate origin x-coordinate

uint16_t origin_y - The desired zone plate origin y-coordinate

uint16_t coarse_factor - The coarse scaling coefficient of the zone plate

uint16_t fine_factor - The fine-tune scaling coefficient of the zone plate

Description

Structure to contain all necessary information about a single instance of the zone plate pattern.

struct intel_vvp_adv_digital_clock_settings

Members

uint8_t config_bits - Control bits to pause or reset the display of the digital clock

uint16_t background_b - The desired digital clock background color (B/Cb component)

uint16_t background_g - The desired digital clock background color (G/Y component)

uint16_t background_r - The desired digital clock background color (R/Cr component) uint16_t font_b - The desired digital clock font color (B/Cb component)

uint16_t font_g - The desired digital clock font color (G/Y component)

uint16_t font_r - The desired digital clock font color (R/Cr component)

uint16_t location_x - The desired digital clock position x-coordinate

uint16_t location_y - The desired digital clock position y-coordinate

uint16_t scale_factor - The digital clock scaling multiplier

uint16_t fps - The value for the digital clock to determine after how many fields one second passes

Description

Structure to contain all necessary information about a single instance of the digital clock pattern.

intel_vvp_adv_tpg_init

Prototype 
int intel_vvp_adv_tpg_init(intel_vvp_adv_tpg_instance *instance, intel_vvp_core_base base);
Description

Initializes an Advanced Test Pattern Generator instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store IP compile-time parameterization. The instance does not fully initialize and should not be used by the application if returning a non-zero error code.

Arguments

instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure

base - base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success; a negative error code in case of error

kIntelVvpCoreVidErr if the vendor ID of the IP is not the IntelFPGA vendor ID (0x6AF7)

kIntelVvpCorePidErr if the product_id does not match with the Advanced Test Pattern Generator product ID (0x0252)

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpAdvTpgRegMapVerisonErr if the register map is not supported

intel_vvp_adv_tpg_get_lite_mode

Prototype 
bool intel_vvp_adv_tpg_get_lite_mode(intel_vvp_adv_tpg_instance *instance);
Description

Returns the value of the LITE_MODE register. The instance must be a fully initialized valid intel_vvp_adv_tpg_instance

Arguments

instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure

Returns

true if the IP is in lite mode; false otherwise

intel_vvp_adv_tpg_get_debug_enabled

Prototype 
bool intel_vvp_adv_tpg_get_debug_enabled(intel_vvp_adv_tpg_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a fully initialized valid intel_vvp_adv_tpg_instance

Arguments

instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure

Returns

true if debug features is on; false otherwise

intel_vvp_adv_tpg_get_bits_per_sample

Prototype 
uint8_t intel_vvp_adv_tpg_get_bps(intel_vvp_adv_tpg_instance *instance);
Description

Returns the value of the BPS register.

Arguments

instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure

Returns

The number of bits per color sample set at compile time

intel_vvp_adv_tpg_get_pixels_in_parallel

Prototype 
uint8_t intel_vvp_adv_tpg_get_pixels_in_parallel(intel_vvp_adv_tpg_instance *instance);
Description

Returns the value of the PIXELS_IN_PARALLEL register. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.

Arguments

instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure

Returns

The number of pixels generated in parallel per clock cycle

intel_vvp_adv_tpg_get_color_space

Prototype 
eIntelVvpAdvTpgColorSpace intel_vvp_adv_tpg_get_color_space(intel_vvp_adv_tpg_instance *instance);
Description

Returns the color space that the IP has been configured with. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.

Arguments

instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure

Returns

eIntelVvpAdvTpgColorSpace corresponding to the color space and subsampling used across all patterns.

intel_vvp_adv_tpg_get_pattern_type

Prototype 
eIntelVvpAdvTpgPatternType intel_vvp_adv_tpg_get_pattern_type(intel_vvp_adv_tpg_instance *instance, int pattern_num);
Description

Arguments

Returns

Prototype 
 
    
 
    

      Description 
    
 
    
 
     
Returns the pattern type of a given pattern number. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
 pattern_num - The pattern number to query. 
 
     
eIntelVvpAdvTpgPatternType corresponding to the queried pattern number 
 
     
kIntelVvpAdvTpgInvalidPattern if pattern_num is greater than or equal to the number of patterns. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_num_patterns 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_get_num_patterns(intel_vvp_adv_tpg_instance *instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns the value of the NUM_PATTERNS register, that is the number of patterns enabled at compile-time. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
The number of patterns configured at compile time
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_commit_writes 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_commit_writes(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Commit all outstanding writes before starting the next field. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
Returns kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_status 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_get_status(intel_vvp_adv_tpg_instance *instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns the value of the STATUS register. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.
 
    
 
    

      Arguments 
    
 
    
 
     
 instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
The value read from the STATUS register
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_is_running 
 
   
 
    

      Prototype 
    
 
    
 
     
bool intel_vvp_adv_tpg_is_running(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns the running bit of the STATUS register, where true indicates that the IP is running. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
True if the IP is currently generating an output field, false if between fields or the IP stops.
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_commit_status 
 
   
 
    

      Prototype 
    
 
    
 
     
bool intel_vvp_adv_tpg_get_commit_status(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns the commit pending bit of the STATUS register, where true indicates that there are outstanding register writes. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
True if you have outstanding writes to the IP, false once you commit all write.
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_enable 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_enable(intel_vvp_adv_tpg_instance* instance, bool enabled);
 
    
 
    

      Description 
    
 
    
 
     
Start or stop the IP after the current field. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
enabled - True to start the IP and generate fields, false to stop the IP after the current field.
 
    
 
    

      Returns 
    
 
    
 
     
Returns kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_is_enabled 
 
   
 
    

      Prototype 
    
 
    
 
     
bool intel_vvp_adv_tpg_is_enabled(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns whether the IP is enabled. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features is on. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
True if the IP is enabled (started), false if the IP is stopped or instance is invalid or debug features is off.
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_start 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_start(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Start the IP; alias for intel_vvp_adv_tpg_enable(instance, true). The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_stop 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_stop(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Stop the IP after the current field; alias for intel_vvp_adv_tpg_enable(instance, false). The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_fields_since_last_start 
 
   
 
    

      Prototype 
    
 
    
 
     
uint32_t intel_vvp_adv_tpg_get_fields_since_last_start(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns the number of fields the IP generates since it last started. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
The number of fields generated since the IP was last started (or 0xFFFFFFFF if instance is null).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_field_width 
 
   
 
    

      Prototype 
    
 
    
 
     
uint32_t intel_vvp_adv_tpg_get_field_width(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured width of generated fields. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features must be enabled. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
The field width (or 0xFFFFFFFF if instance is null and debug features is off).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_set_field_width 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_field_width(intel_vvp_adv_tpg_instance* instance, uint32_t width);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured width of generated fields. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null or debug features is off. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_field_height 
 
   
 
    

      Prototype 
    
 
    
 
     
uint32_t intel_vvp_adv_tpg_get_field_height(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured height of generated fields. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features must be on. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
The field height (or 0xFFFFFFFF if instance is null and debug features is off).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_set_field_height 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_field_height(intel_vvp_adv_tpg_instance* instance, int32_t height);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured width of generated fields. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    
 
     
height - The desired field height
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null or debug features is off. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_field_interlace 
 
   
 
    

      Prototype 
    
 
    
 
     
uint8_t intel_vvp_adv_tpg_get_field_interlace(intel_vvp_adv_tpg_instance* instance);
 
    
 
    

      Description 
    
 
    
 
     
Returns the set interlace configuration of generated fields. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features must be on. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
    
 
    

      Returns 
    
 
    
 
     
The field width (or 0xFF if instance is null and debug features is off).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_set_field_interlace 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_field_interlace(intel_vvp_adv_tpg_instance* instance, uint8_t interlace);
 
    
 
    

      Description 
    
 
    
 
     
Set the interlace configuration of generated fields and the value to populate the interlace nibble in image information metapackets. Write 0-7 for progressive output, 8-11 for F0 first interlaced output, and 12-15 for F1 first interlaced output. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
interlace - The desired interlace configuration/nibble 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null or debug features is off. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_pattern_width 
 
   
 
    

      Prototype 
    
 
    
 
     
uint32_t intel_vvp_adv_tpg_get_pattern_width(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured width of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features must be on. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
     
pattern_num – The pattern number to query
 
    
 
    

      Returns 
    
 
    
 
     
The configured pattern width (or 0xFFFFFFFF if instance is null/ or debug features is off or pattern_num is 0).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_set_pattern_width 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_pattern_width(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, uint32_t width);
 
    
 
    

      Description 
    
 
    
 
     
Set the width of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern. 
 
     
width - The desired width to configure a pattern with 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_pattern_height 
 
   
 
    

      Prototype 
    
 
    
 
     
uint32_t intel_vvp_adv_tpg_get_pattern_height(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured height of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features must be on. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number to query 
 
    
 
    

      Returns 
    
 
    
 
     
The configured pattern height (or 0xFFFFFFFF if instance is null or debug features is off or pattern_num is 0).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_set_pattern_height 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_pattern_height(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, uint32_t height);
 
    
 
    

      Description 
    
 
    
 
     
Set the height of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance.
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern. 
 
     
height - The desired height to configure a pattern with 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_pattern_alpha 
 
   
 
    

      Prototype 
    
 
    
 
     
uint16_t intel_vvp_adv_tpg_get_pattern_alpha(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured alpha value (opacity) of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features must be on. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
     
 pattern_num - The pattern number to query
 
    
 
    

      Returns 
    
 
    
 
     
The configured pattern alpha (or 0xFFFF if instance is null or debug features is off or pattern_num is 0).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_set_pattern_alpha 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_pattern_alpha(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, uint16_t alpha);
 
    
 
    

      Description 
    
 
    
 
     
Set the alpha value (opacity) of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern. 
 
     
alpha - The desired alpha to configure a pattern with 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgColorErr if alpha is greater than the maximum allowed by the bits per color sample 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_pattern_horiz_offset 
 
   
 
    

      Prototype 
    
 
    
 
     
uint32_t intel_vvp_adv_tpg_get_pattern_horiz_offset(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured horizontal offset (from the left) of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features must be on. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
     
 pattern_num - The pattern number to query 
 
    
 
    

      Returns 
    
 
    
 
     
The configured pattern horizontal offset (or 0xFFFFFFFF if instance is null or debug features is off or pattern_num is 0).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_set_pattern_horiz_offset 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_pattern_horiz_offset(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, uint32_t h_offset);
 
    
 
    

      Description 
    
 
    
 
     
Set the horizontal offset (from the left) of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern. 
 
     
h_offset - The desired horizontal offset to configure a pattern with 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_get_pattern_vert_offset 
 
   
 
    

      Prototype 
    
 
    
 
     
uint32_t intel_vvp_adv_tpg_get_pattern_vert_offset(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num);
 
    
 
    

      Description 
    
 
    
 
     
Returns the configured vertical offset (from the top) of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance, and debug features must be on. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
     
pattern_num - The pattern number to query
 
    
 
    

      Returns 
    
 
    
 
     
The configured pattern vertical offset (or 0xFFFFFFFF if instance is null and debug features is off and pattern_num is 0).
 
    
 
   
 
  
 
  
 
   
 intel_vvp_adv_tpg_set_pattern_vert_offset 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_pattern_vert_offset(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, uint32_t v_offset);
 
    
 
    

      Description 
    
 
    
 
     
Set the vertical offset (from the top) of a given pattern excluding pattern 0. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern. 
 
     
v_offset - The desired vertical offset to configure a pattern with 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns. 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_tpg_set_bars_type 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_bars_type(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, eIntelVvpAdvTpgBarsType bar_type);
 
    
 
    

      Description 
    
 
    
 
     
Selects the type of color bars (black/white, grey, color, mixed) of a given pattern of type kIntelVvpAdvTpgBarsPattern. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure
 
     
pattern_num - The pattern number corresponding to the desired pattern 
 
     
 bar_type - The type of bars pattern
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns, or if the pattern_num does not correspond to a pattern of type 
 
     
kIntelVvpAdvTpgBarsPattern 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_tpg_set_constant_colors 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_constant_colors(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, uint16_t color1, uint16_t color2, uint16_t color3);
 
    
 
    

      Description 
    
 
    
 
     
Set the color of a given pattern of type kIntelVvpAdvTpgConstantColorPattern. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern 
 
     
color1, color2, color3 - The new color sample values 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns, or if the pattern_num does not correspond to a pattern of type 
 
     
kIntelVvpAdvTpgConstantColorPattern 
 
     
kIntelVvpAdvTpgColorErr if any of the provided color sample values are greater than the maximum allowed by the bits per color sample 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_tpg_set_zone_plate_settings 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_zone_plate_settings(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, uint16_t x_coord, uint16_t y_coord, uint16_t coarse_factor, uint16_t fine_tune_factor);
 
    
 
    

      Description 
    
 
    
 
     
Configure the scaling and origin coordinates of a given pattern of type kIntelVvpAdvTpgZonePlatePattern. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern 
 
     
x_coord, y_coord - The coordinates of the zone plate origin 
 
     
coarse_factor - The coarse scaling coefficient of the zone plate 
 
     
fine_tune_factor - The fine-tune scaling coefficient of the zone plate; this is a 16-bit fixed point number with 8 fractional bits. 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns, or if the pattern_num does not correspond to a pattern of type 
 
     
kIntelVvpAdvTpgZonePlatePattern 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_tpg_set_zone_plate_settings_s 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_zone_plate_settings_s(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, intel_vvp_adv_tpg_zone_plate_settings *settings_struct);
 
    
 
    

      Description 
    
 
    
 
     
Configure the scaling and origin coordinates of a given pattern of type kIntelVvpAdvTpgZonePlatePattern. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern 
 
     
settings_struct - Pointer to the struct containing zone plate configuration 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns, or if the pattern_num does not correspond to a pattern of type 
 
     
kIntelVvpAdvTpgZonePlatePattern 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_tpg_set_digital_clock_settings 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_digital_clock_settings(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, uint8_t config_bits, uint16_t background_r, uint16_t background_g, uint16_t background_b, uint16_t font_r, uint16_t font_g, uint16_t font_b, uint16_t location_x, uint16_t location_y, uint16_t scale_factor, uint8_t fps);
 
    
 
    

      Description 
    
 
    
 
     
Configure colors, location, size and control values of a given pattern of type kIntelVvpAdvTpgDigitalClockPattern using the helper struct. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern 
 
     
config_bits - Set bit 0 to pause the digital display, set bit 1 to reset the digital display 
 
     
background_b, background_g, background_r - The background color samples 
 
     
font_b, font_g, font_r - The font color samples 
 
     
location_x, location_y - The location for the digital clock display 
 
     
scale_factor - The digital display sizing coefficient. If 1, the display ix 88x8 pixels. 
 
     
fps - The number of frames the IP generates for one second to has elapsed. 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns, or if the pattern_num does not correspond to a pattern of type 
 
     
kIntelVvpAdvTpgDigitalClockPattern 
 
     
kIntelVvpAdvTpgColorErr if any of the background or font color samples are greater than the maximum allowed by the bits per color sample 
 
    
 
   
 
  
 
  
 
   
 intel_vvp_tpg_set_digital_clock_settings_s 
 
   
 
    

      Prototype 
    
 
    
 
     
int intel_vvp_adv_tpg_set_digital_clock_settings_s(intel_vvp_adv_tpg_instance* instance, uint8_t pattern_num, intel_vvp_adv_tpg_digital_clock_settings *settings_struct);
 
    
 
    

      Description 
    
 
    
 
     
Configure colors, location, size and control values of a given pattern of type kIntelVvpAdvTpgDigitalClockPattern using the helper struct. The instance must be a valid and initialized instance of intel_vvp_adv_tpg_instance. 
 
    
 
    

      Arguments 
    
 
    
 
     
instance - pointer to the intel_vvp_adv_tpg_instance software driver instance structure 
 
     
pattern_num - The pattern number corresponding to the desired pattern 
 
     
settings_struct - Pointer to the struct containing the digital clock configuration 
 
    
 
    

      Returns 
    
 
    
 
     
kIntelVvpCoreOk (0) in case of success. 
 
     
kIntelVvpCoreInstanceErr if the instance is null. 
 
     
kIntelVvpAdvTpgPatternZeroErr if pattern_num is 0 
 
     
kIntelVvpAdvTpgInvalidPatternErr if pattern_num is greater or equal to the number of patterns, or if the pattern_num does not correspond to a pattern of type 
 
     
kIntelVvpAdvTpgZonePlatePattern 
 
     
kIntelVvpAdvTpgColorErr if any of the background or font color samples are greater than the maximum allowed by the bits per color sample 
 
    
 
   
 
  
 
 
 
 
 
  

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