Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel® FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Text Box Intel® FPGA IP 43. Tone Mapping Operator Intel® FPGA IP 44. Test Pattern Generator Intel® FPGA IP 45. Unsharp Mask Intel® FPGA IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer Intel® FPGA IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO Intel® FPGA IP 51. Video Timing Generator Intel® FPGA IP 52. Vignette Correction Intel® FPGA IP 53. Warp Intel® FPGA IP 54. White Balance Correction Intel® FPGA IP 55. White Balance Statistics Intel® FPGA IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. Adaptive Noise Reduction Intel® FPGA IP x
10.1. About the Adaptive Noise Reduction IP 10.2. Adaptive Noise Reduction IP Parameters 10.3. Adaptive Noise Reduction IP Functional Description 10.4. Adaptive Noise Reduction IP Registers 10.5. Adaptive Noise Reduction IP Software API
10.1. About the Adaptive Noise Reduction IP x
10.1.1. Adaptive Noise Reduction IP Performance and Resources
10.3. Adaptive Noise Reduction IP Functional Description x
10.3.1. Adaptive Noise Reduction IP Interfaces
11. Advanced Test Pattern Generator Intel® FPGA IP x
11.1. About the Advanced Test Pattern Generator IP 11.2. Advanced Test Pattern Generator IP Parameters 11.3. Advanced Test Pattern Generator IP Functional Description 11.4. Advanced Test Pattern Generator IP Registers 11.5. Advanced Test Pattern Generator IP Software API
11.1. About the Advanced Test Pattern Generator IP x
11.1.1. Advanced Test Pattern Generator IP Performance and Resources
11.3. Advanced Test Pattern Generator IP Functional Description x
11.3.1. Test Patterns 11.3.2. Dimensions, Offsets, and Alpha Settings 11.3.3. Run-time Settings 11.3.4. Advanced Test Pattern Generator IP Interfaces
12. AXI-Stream Broadcaster Intel® FPGA IP x
12.1. About the AXI-Stream Broadcaster IP 12.2. AXI-Stream Broadcaster IP Parameters 12.3. AXI-Stream Broadcaster IP Interfaces
12.1. About the AXI-Stream Broadcaster IP x
12.1.1. AXI-Stream Broadcaster IP Features 12.1.2. AXI-Stream Broadcaster IP Performance and Resources
13. Bits per Color Sample Adapter Intel® FPGA IP x
13.1. About the Bits per Color Sample Adapter IP 13.2. Bits per Color Sample Adapter IP Parameters 13.3. Bits per Color Sample Adapter IP Dithering Functional Description 13.4. Bits per Color Sample Adapter IP Registers 13.5. Bits per Color Sample Adapter Software API
13.1. About the Bits per Color Sample Adapter IP x
13.1.1. Bits per Color Sample Adapter IP Performance and Resources
13.3. Bits per Color Sample Adapter IP Dithering Functional Description x
13.3.1. Bits per Color Sample Adapter IP Interfaces
14. Black Level Correction Intel® FPGA IP x
14.1. About the Black Level Correction IP 14.2. Black Level Correction IP Parameters 14.3. Black Level Correction IP Functional Description 14.4. Black Level Correction IP Registers 14.5. Black Level Correction IP Software API
14.1. About the Black Level Correction IP x
14.1.1. Black Level Correction IP Performance and Resources
14.3. Black Level Correction IP Functional Description x
14.3.1. Black Level Correction IP Interfaces
15. Black Level Statistics Intel® FPGA IP x
15.1. About the Black Level Statistics IP 15.2. Black Level Statistics IP Parameters 15.3. Black Level Statistics IP Interfaces 15.4. Black Level Statistics IP Registers 15.5. Black Level Statistics IP Software API
15.1. About the Black Level Statistics IP x
15.1.1. Black Level Statistics IP Performance and Resources
16. Chroma Key Intel® FPGA IP x
16.1. About the Chroma Key IP 16.2. Chroma Key IP Parameters 16.3. Chroma Key IP Interfaces 16.4. Chroma Key Replacement 16.5. Chroma Key IP Registers 16.6. Chroma Key IP Software API
16.1. About the Chroma Key IP x
16.1.1. Chroma Key IP Performance and Resources
17. Chroma Resampler Intel® FPGA IP x
17.1. About the Chroma Resampler IP 17.2. Chroma Resampler IP Parameters 17.3. Chroma Resampler IP Functional Description 17.4. Chroma Resampler IP Registers 17.5. Chroma Resampler IP Software API
17.1. About the Chroma Resampler IP x
17.1.1. Chroma Resampler Performance and Resources
17.3. Chroma Resampler IP Functional Description x
17.3.1. Chroma Resampler IP Interfaces
18. Clipper Intel® FPGA IP x
18.1. About the Clipper IP 18.2. Clipper IP Parameters 18.3. Clipper IP Interfaces 18.4. Clipper IP Registers 18.5. Clipper IP Software API
18.1. About the Clipper IP x
18.1.1. Clipper IP Performance and Resources
19. Clocked Video Input Intel® FPGA IP x
19.1. About the Clocked Video Input IP 19.2. Initializing the Clocked Video Input IP 19.3. Clocked Video Input IP Parameters 19.4. Clocked Video Input IP Interfaces 19.5. Clocked Video Input IP Registers 19.6. Clocked Video Input IP Software API
19.1. About the Clocked Video Input IP x
19.1.1. Clocked Video Input IP Features 19.1.2. Clocked Video Input IP Performance and Resources
20. Clocked Video to Full-Raster Converter Intel® FPGA IP x
20.1. About the Clocked Video to Full-Raster Converter IP 20.2. Clocked Video to Full-Raster Converter Parameters 20.3. Clocked Video to Full-Raster Converter Block Description 20.4. Clocked Video Converter to Full-Raster IP Registers
20.1. About the Clocked Video to Full-Raster Converter IP x
20.1.1. Clocked Video to Full-Raster Converter Features 20.1.2. Clocked Video to Full-Raster Converter Performance and Resources
20.3. Clocked Video to Full-Raster Converter Block Description x
20.3.1. Clocked Video to Full-Raster Converter Interfaces
21. Clocked Video Output Intel® FPGA IP x
21.1. About the Clocked Video Output IP 21.2. Clocked Video Output IP Parameters 21.3. Clocked Video Output IP Functional Description 21.4. Clocked Video Output IP Interfaces 21.5. Clocked Video Output IP Registers 21.6. Clocked Video Output IP Software API
21.1. About the Clocked Video Output IP x
21.1.1. Clocked Video Output IP Performance and Resources 21.1.2. Clocked Video Output IP Features
22. Color Plane Manager Intel® FPGA IP x
22.1. About the Color Plane Manager IP 22.2. Color Plane Manager IP Parameters 22.3. Color Plane Manager IP Functional Description 22.4. Color Plane Manager IP Registers 22.5. Color Plane Manager Software API
22.1. About the Color Plane Manager IP x
22.1.1. Color Plane Manager IP Performance and Resources
22.3. Color Plane Manager IP Functional Description x
22.3.1. Color Plane Manager IP Interfaces
23. Color Space Converter Intel® FPGA IP x
23.1. About the Color Space Converter IP 23.2. Color Space Converter IP Parameters 23.3. Color Space Converter IP Functional Description 23.4. Color Space Converter IP Registers 23.5. Color Space Converter IP Software API
23.1. About the Color Space Converter IP x
23.1.1. Color Space Converter IP Features 23.1.2. Color Space Converter IP Performance and Resources
23.3. Color Space Converter IP Functional Description x
23.3.1. Color Space Converter IP Interfaces
24. Defective Pixel Correction Intel® FPGA IP x
24.1. About the Defective Pixel Correction IP 24.2. Defective Pixel Correction IP Parameters 24.3. Defective Pixel Correction IP Functional Description 24.4. Defective Pixel Correction IP Registers 24.5. Defective Pixel Correction IP Software API
24.1. About the Defective Pixel Correction IP x
24.1.1. Defective Pixel Correction IP Performance and Resources
24.3. Defective Pixel Correction IP Functional Description x
24.3.1. Defective Pixel Correction IP Interfaces
25. Deinterlacer Intel® FPGA IP x
25.1. About the Deinterlacer IP 25.2. Deinterlacer Parameters 25.3. Deinterlacer IP Functional Description 25.4. Deinterlacer IP Registers 25.5. Deinterlacer IP Software API
25.1. About the Deinterlacer IP x
25.1.1. Deinterlacer Performance and Resources
25.3. Deinterlacer IP Functional Description x
25.3.1. Deinterlacer Interfaces
26. Demosaic Intel® FPGA IP x
26.1. About the Demosaic IP 26.2. Demosaic IP Parameters 26.3. Demosaic IP Functional Description 26.4. Demosaic IP Registers 26.5. Demosaic IP Software API
26.1. About the Demosaic IP x
26.1.1. Demosaic IP Performance and Resources
26.3. Demosaic IP Functional Description x
26.3.1. Demosaic IP Interfaces
27. FIR Filter Intel® FPGA IP x
27.1. About the FIR Filter 27.2. FIR Filter Parameters 27.3. FIR Filter IP Operation 27.4. FIR Filter Interfaces 27.5. FIR Filter Registers 27.6. FIR Filter IP Software API
27.1. About the FIR Filter x
27.1.1. FIR Filter IP Performance and Resources
27.3. FIR Filter IP Operation x
27.3.1. FIR Filter Processing 27.3.2. FIR Filter Precision 27.3.3. FIR Coefficient Specification 27.3.4. FIR Filter Symmetry 27.3.5. Result to Output Data Type Conversion
27.3.4. FIR Filter Symmetry x
27.3.4.1. No Symmetry 27.3.4.2. Horizontal Symmetry 27.3.4.3. Vertical Symmetry 27.3.4.4. Horizontal and Vertical Symmetry 27.3.4.5. Diagonal Symmetry
28. Frame Cleaner Intel® FPGA IP x
28.1. About the Frame Cleaner IP 28.2. Frame Cleaner IP Parameters 28.3. Frame Cleaner IP Functional Description 28.4. Frame Cleaner IP Interfaces 28.5. Frame Cleaner IP Registers 28.6. Frame Cleaner IP Software API
28.1. About the Frame Cleaner IP x
28.1.1. Frame Cleaner IP Performance and Resources
29. Full-Raster to Clocked Video Converter Intel® FPGA IP x
29.1. About the Full-Raster to Clocked Video Converter 29.2. Full Raster to Clocked Video Converter Parameters 29.3. Full-Raster to Clocked Video Converter Block Description 29.4. Full-Raster to Clocked Video Converter Registers
29.1. About the Full-Raster to Clocked Video Converter x
29.1.1. Full-Raster to Clocked Video Converter Features 29.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
29.3. Full-Raster to Clocked Video Converter Block Description x
29.3.1. Full Raster to Clocked Video Converter Interfaces
30. Full-Raster to Streaming Converter Intel® FPGA IP x
30.1. About the Full-Raster to Streaming Converter IP 30.2. Full-Raster to Streaming Converter Parameters 30.3. Full-Raster to Streaming Converter Block Description
30.1. About the Full-Raster to Streaming Converter IP x
30.1.1. Full-Raster to Streaming Converter Features 30.1.2. Full-Raster to Streaming Converter Performance and Resources
30.3. Full-Raster to Streaming Converter Block Description x
30.3.1. Full-Raster to Streaming Converter Interfaces
31. Genlock Controller Intel® FPGA IP x
31.1. About the Genlock Controller IP 31.2. Genlock Controller IP Parameters 31.3. Genlock Controller IP Functional Description 31.4. Using Genlock Controller IP Software 31.5. Genlock Controller IP Registers 31.6. Genlock Controller IP Software API
31.1. About the Genlock Controller IP x
31.1.1. Genlock Controller IP Performance and Resources
31.3. Genlock Controller IP Functional Description x
31.3.1. Genlock Controller IP Interfaces
31.4. Using Genlock Controller IP Software x
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 31.4.3. Setting the VCXO hold over 31.4.4. Restarting the Genlock Controller IP 31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 31.4.7. Disturbing a Reference Clock (a cable pull)
32. Generic Crosspoint Intel® FPGA IP x
32.1. About the Generic Crosspoint IP 32.2. Generic Crosspoint IP Parameters 32.3. Generic Crosspoint IP Interfaces 32.4. Generic Crosspoint IP Registers 32.5. Generic Crosspoint IP Software API
32.1. About the Generic Crosspoint IP x
32.1.1. Generic Crosspoint IP Features 32.1.2. Generic Crosspoint Performance and Resources
33. Genlock Signal Router Intel® FPGA IP x
33.1. About the Genlock Signal Router IP 33.2. Genlock Signal Router IP Parameters 33.3. Genlock Signal Router IP Interfaces 33.4. Genlock Signal Router IP Registers 33.5. Genlock Signal Router IP Software API
33.1. About the Genlock Signal Router IP x
33.1.1. Genlock Signal Router IP Features 33.1.2. Genlock Signal Router IP Performance and Resources
34. Guard Bands Intel® FPGA IP x
34.1. About the Guard Bands IP 34.2. Guard Bands IP Parameters 34.3. Guard Bands IP Interfaces 34.4. Guard Bands IP Registers 34.5. Guard Bands IP Software API
34.1. About the Guard Bands IP x
34.1.1. Guard Bands IP Performance and Resources
35. Histogram Statistics Intel® FPGA IP x
35.1. About the Histogram Statistics IP 35.2. Histogram Statistics IP Parameters 35.3. Histogram Statistics IP Interfaces 35.4. Histogram Statistics IP Registers 35.5. Histogram Statistics IP Software API
35.1. About the Histogram Statistics IP x
35.1.1. Histogram Statistics IP Performance and Resources
36. Interlacer Intel® FPGA IP x
36.1. About the Interlacer IP 36.2. Interlacer IP Parameters 36.3. Interlacer IP Functional Description 36.4. Interlacer IP Registers 36.5. Interlacer IP Software API
36.1. About the Interlacer IP x
36.1.1. Interlacer IP Performance and Resources
36.3. Interlacer IP Functional Description x
36.3.1. Interlacer IP Interfaces
37. Mixer Intel® FPGA IP x
37.1. About the Mixer IP 37.2. Mixer IP Parameters 37.3. Mixer IP Functional Description 37.4. Mixer IP Registers 37.5. Mixer IP Software API
37.1. About the Mixer IP x
37.1.1. Mixer IP Performance and Resources
37.3. Mixer IP Functional Description x
37.3.1. Mixer IP Interfaces
38. Pixels in Parallel Converter Intel® FPGA IP x
38.1. About the Pixels in Parallel Converter IP 38.2. Pixels in Parallel Converter IP Parameters 38.3. Pixels in Parallel Converter Interfaces 38.4. Pixels in Parallel Converter Registers 38.5. Pixels in Parallel Converter IP Software API
38.1. About the Pixels in Parallel Converter IP x
38.1.1. Pixels in Parallel Converter IP Performance and Resources
39. Scaler Intel® FPGA IP x
39.1. About the Scaler 39.2. Scaler IP Parameters 39.3. Scaler IP Functional Description 39.4. Scaler IP Registers 39.5. Scaler IP Software API
39.1. About the Scaler x
39.1.1. Scaler IP Performance and Resources
39.2. Scaler IP Parameters x
39.2.1. Scaler Maximum Resolution
39.3. Scaler IP Functional Description x
39.3.1. Coefficient Selection 39.3.2. Coefficient Quantization 39.3.3. Filter Behavior at Edge Boundaries 39.3.4. Partial Frame Scaling 39.3.5. 422 and 420 Chroma Sampled Data Scaling 39.3.6. Scaler IP Interfaces
39.3.1. Coefficient Selection x
39.3.1.1. Updating Scaler IP Runtime Coefficients
40. Stream Cleaner Intel® FPGA IP x
40.1. About the Stream Cleaner IP 40.2. Stream Cleaner IP Parameters 40.3. Stream Cleaner IP Functional Description
40.1. About the Stream Cleaner IP x
40.1.1. Stream Cleaner IP Performance and Resources
40.3. Stream Cleaner IP Functional Description x
40.3.1. Stream Cleaner IP Interfaces
41. Switch Intel® FPGA IP x
41.1. About the Switch IP 41.2. Switch IP Parameters 41.3. Switch IP Functional Description 41.4. Switch IP Registers 41.5. Switch IP Software API
41.1. About the Switch IP x
41.1.1. Switch IP Performance and Resources
41.3. Switch IP Functional Description x
41.3.1. Switch IP Latency 41.3.2. Switch IP Interfaces
42. Text Box Intel® FPGA IP x
42.1. About the Text Box IP 42.2. Text Box IP Parameters 42.3. Text Box IP Functional Description 42.4. Text Box IP Registers 42.5. Text Box IP Software API
42.1. About the Text Box IP x
42.1.1. Text Box IP Performance and Resources
42.3. Text Box IP Functional Description x
42.3.1. Writing Text at Run Time with Double Buffering 42.3.2. Writing Text at Run Time without Double Buffering 42.3.3. Text Box IP Interfaces
43. Tone Mapping Operator Intel® FPGA IP x
43.1. About the Tone Mapping Operator IP 43.2. TMO IP Parameters 43.3. TMO IP Block Description 43.4. TMO IP Registers 43.5. TMO IP Software API
43.1. About the Tone Mapping Operator IP x
43.1.1. TMO IP Features 43.1.2. TMO IP Performance and Resource Utilization
43.3. TMO IP Block Description x
43.3.1. TMO IP Interfaces 43.3.2. TMO IP Latency
44. Test Pattern Generator Intel® FPGA IP x
44.1. About the Test Pattern Generator IP 44.2. Test Pattern Generator IP Parameters 44.3. Test Pattern Generator IP Functional Description 44.4. Test Pattern Generator IP Registers 44.5. Test Pattern Generator IP Software API
44.1. About the Test Pattern Generator IP x
44.1.1. Test Pattern Generator IP Performance and Resources
44.3. Test Pattern Generator IP Functional Description x
44.3.1. Test Patterns 44.3.2. Output Subsampling and Color Space 44.3.3. Run-time Settings 44.3.4. Test Pattern Generator IP Interfaces
45. Unsharp Mask Intel® FPGA IP x
45.1. About the Unsharp Mask IP 45.2. Unsharp Mask IP Parameters 45.3. Unsharp Mask IP Functional Description 45.4. Unsharp Mask IP Registers 45.5. Unsharp Mask IP Software API
45.1. About the Unsharp Mask IP x
45.1.1. Unsharp Mask IP Performance and Resources
45.3. Unsharp Mask IP Functional Description x
45.3.1. Unsharp Mask IP Interfaces
46. Video and Vision Monitor Intel FPGA IP x
46.1. About the Video and Vision Monitor IP 46.2. Video and Vision Monitor IP Parameters 46.3. Video and Vision Monitor IP Functional Description 46.4. Video and Vision Monitor IP Registers 46.5. Video and Vision Monitor Software API
46.1. About the Video and Vision Monitor IP x
46.1.1. Video and Vision Monitor IP Performance and Resources
46.3. Video and Vision Monitor IP Functional Description x
46.3.1. Video and Vision Monitor IP Interfaces
47. Video Frame Buffer Intel® FPGA IP x
47.1. About the Video Frame Buffer IP 47.2. Video Frame Buffer IP Parameters 47.3. Video Frame Buffer IP Functional Description 47.4. Video Frame Buffer IP Registers 47.5. Video Frame Buffer IP Software API
47.1. About the Video Frame Buffer IP x
47.1.1. Video Frame Buffer Performance and Resources
47.3. Video Frame Buffer IP Functional Description x
47.3.1. Video Frame Buffer IP Interfaces
48. Video Frame Reader Intel FPGA IP x
48.1. About the Video Frame Reader IP 48.2. Video Frame Reader IP Parameters 48.3. Video Frame Reader IP Functional Description 48.4. Video Frame Reader IP Registers 48.5. Video Frame Reader IP Software API
48.1. About the Video Frame Reader IP x
48.1.1. Video Frame Reader IP Performance and Resources
48.3. Video Frame Reader IP Functional Description x
48.3.1. Video Frame Reader IP Interfaces
49. Video Frame Writer Intel FPGA IP x
49.1. About the Video Buffer Writer IP 49.2. Video Frame Writer IP Parameters 49.3. Video Frame Writer IP Functional Description 49.4. Video Frame Writer IP Registers 49.5. Video Frame Writer IP Software API
49.1. About the Video Buffer Writer IP x
49.1.1. Video Frame Writer IP Performance and Resources
49.3. Video Frame Writer IP Functional Description x
49.3.1. Video Frame Writer IP Interfaces
50. Video Streaming FIFO Intel® FPGA IP x
50.1. About the Video Streaming FIFO IP 50.2. Video Streaming FIFO IP Parameters 50.3. Video Streaming FIFO IP Interfaces
50.1. About the Video Streaming FIFO IP x
50.1.1. Video Streaming FIFO IP Performance and Resources
51. Video Timing Generator Intel® FPGA IP x
51.1. About the Video Timing Generator IP 51.2. Video Timing Generator IP Parameters 51.3. Video Timing Generator IP Functional Description 51.4. Video Timing Generator IP Interfaces 51.5. Video Timing Generator IP Registers 51.6. Video Timing Generator IP Software API
51.1. About the Video Timing Generator IP x
51.1.1. Video Timing Generator IP Features 51.1.2. Video Timing Generator IP Performance and Resources
52. Vignette Correction Intel® FPGA IP x
52.1. About the Vignette Correction IP 52.2. Vignette Correction IP Parameters 52.3. Vignette Correction IP Interfaces 52.4. Vignette Correction IP Registers 52.5. Vignette Correction IP Software API
52.1. About the Vignette Correction IP x
52.1.1. Vignette Correction IP Performance and Resources
53. Warp Intel® FPGA IP x
53.1. About the Warp IP 53.2. Warp IP Parameters 53.3. Warp IP Block Description 53.4. Warp IP Registers 53.5. Warp IP Software API
53.1. About the Warp IP x
53.1.1. Warp IP Features 53.1.2. Warp IP Performance and Resource Utilization
53.3. Warp IP Block Description x
53.3.1. Block Cache Tool 53.3.2. Warp IP Interfaces 53.3.3. Warp IP Latency 53.3.4. External Memory for Warp IP
53.5. Warp IP Software API x
53.5.1. Using Warp IP Software 53.5.2. Warp IP Software Code Examples
54. White Balance Correction Intel® FPGA IP x
54.1. About the White Balance Correction IP 54.2. White Balance Correction IP Parameters 54.3. White Balance Correction IP Functional Description 54.4. White Balance Correction IP Registers 54.5. White Balance Correction IP Software API
54.1. About the White Balance Correction IP x
54.1.1. White Balance Correction IP Performance and Resources
54.3. White Balance Correction IP Functional Description x
54.3.1. White Balance Correction IP Interfaces
55. White Balance Statistics Intel® FPGA IP x
55.1. About the White Balance Statistics IP 55.2. White Balance Statistics IP Parameters 55.3. White Balance Statistics IP Interfaces 55.4. White Balance Statistics IP Registers 55.5. White Balance Statistics IP Software API
55.1. About the White Balance Statistics IP x
55.1.1. White Balance Statistics IP Performance and Resources
56. Design Security x
56.1. Memory Subsystems 56.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel® FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Text Box Intel® FPGA IP
43. Tone Mapping Operator Intel® FPGA IP
44. Test Pattern Generator Intel® FPGA IP
45. Unsharp Mask Intel® FPGA IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer Intel® FPGA IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO Intel® FPGA IP
51. Video Timing Generator Intel® FPGA IP
52. Vignette Correction Intel® FPGA IP
53. Warp Intel® FPGA IP
54. White Balance Correction Intel® FPGA IP
55. White Balance Statistics Intel® FPGA IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide

7.3. Protocol Converter IP Functional Description

Protocol Converter - Avalon Streaming Video to Intel FPGA Streaming Video Lite

The IP converts the protocol in steps:

  1. Changes the Avalon Streaming ready latency from 1 to 0.

    Avalon Streaming Video specifies a ready latency of 1. The IP converts the ready latency to 0 to match the ready-valid handshake mechanism specified for AXI4-Stream.

  2. Removes all packets other than video packets from the stream.

    Avalon Streaming Video specifies a mechanism to assign a type identifier (a number between 0 and 15) to each packet in the stream. Type-0 packets are frames of pixel data and all other packet types indicate nonvideo data. Packets of type-15 (referred to as metapackets) contain metadata to specify the width, height, and interlacing properties of subsequent type-0 video packets. Intel FPGA Streaming Video lite does not allow for metapackets in the stream. The IP discards all packets with a type that is greater than 0. The IP does not propagate type-15 metapackets that specify the properties of the video. However, it parses them during the discard process to extract the expected width of the video frames that follow. The IP uses this information in the next step of the conversion.

  3. Splits frame packets into line packets.

    Avalon Streaming Video specifies that each video packet contains one cycle of header data followed by all of the pixels required for an interlaced frame or progressive frame of video. The header data specifies the packet type. Intel FPGA Streaming Video requires that each packet is one line of video data (with no header information). The IP strips out incoming Avalon Streaming Video frame packets and then splits them into multiple packets. Each packet contains a single video line. The IP extracts the expected width of the video frame from the discarded metapacket that precedes the frame. The IP uses this value to determine where the incoming frame packet should be split to make each output line packet. The IP replaces the Avalon Streaming startofpacket and endofpacket signals with the AXI4-Stream tlast signal and creates the tuser signal. The IP reformats the incoming Avalon Streaming data to create byte-aligned AXI4-Stream tdata

Avalon streaming video to Intel FPGA streaming video full

Converting Avalon streaming video to Intel FPGA streaming video full is similar to converting to Intel FPGA streaming video lite. Steps 1 and 3 are the same, but step 2 is different because Intel FPGA streaming video full supports nonvideo packets. The nonvideo data in the Avalon streaming video input can be retained and does not need to be discarded.

Nonvideo packets in Intel FPGA streaming video full are indicated by asserting bit 1 of the tuser field on the first cycle of the packet. As with Avalon streaming video, each nonvideo packet in Intel FPGA streaming video full has an associated packet type, which is indicated in the five LSBs of the first beat of data.

Intel FPGA streaming video full requires an image information packet (type 0) that precedes the packets for each video field and followed by an end-of-field packet (type 1). The IP adds these to the incoming stream. The image information packet is similar to the control packet in the Avalon streaming video input. It contains information about the width, height, and interlaced format of the following field, which can be sourced directly from the Avalon streaming video control packet. Further information about the input color space, chroma sampling and siting, which is not in the incoming control packet comes either from the register map or parameters, depending on how you configure the IP.

You can select how the IP processes user packets (types 1-14) in the Avalon streaming video input via the How Avalon-ST Video user packets are handled parameter. You can select that these types of packets never exist, in which case no provision is made in the IP to process them (if any are received the IP may lock-up). You can select that the IP discards these packets, in which case the IP adds some additional logic to detect and discard them, as is the case in conversion to Intel FPGA streaming video lite.

The final option that is not available when converting to Intel FPGA Streaming video lite but is available when converting to Intel FPGA streaming video full, is to propagate the incoming user packets. However, Intel FPGA streaming video full cannot insert the user packet directly into the main video stream as nonvideo packets are restricted to only use 16 bits of the data signal, and to have a maximum length of 4 data beats.

To process larger nonvideo packets, Intel FPGA streaming video includes the option for a separate auxiliary interface, which follows the same protocol as the main video interface. The video packets on the video interface (those with tuser bit 1 set to 0) contain video lines. The data packets on the auxiliary interface may contain any nonvideo data you require. When you select Pass all user packets through to the output for Avalon streaming video user packet handling, the header beat of the Avalon streaming video user packet (which contains the packet type) is clipped from the packet, and the remainder of the data is routed to the auxiliary output interface. To allow the packets on the auxiliary interface to be synchronized with the main video interface, a single beat nonvideo packet is included in the main stream at the point where the user packet was present in the original Avalon streaming video input. Intel FPGA streaming video full sets aside the nonvideo packet types in the range 16-31 for free use by the system. The IP modifies the original Avalon streaming video packet type (in the range 1-14) by adding 16 to move it into the range allowed by Intel streaming video full, and the packet created uses this type. The newly created packet also sets a flag in bit 5 to indicate that a packet on the auxiliary interface is associated with this nonvideo packet. You should read it at this point in the video stream.

Protocol Converter - Intel FPGA Streaming Video Lite to Avalon Streaming Video

The IP converts the protocol in 3 steps.

  1. Combines line packets into a single frame packet.

    Intel FPGA Streaming Video specifies that you transmit video data with one video line per packet. Avalon Streaming Video requires that you transmit all the pixels in a frame in a single packet. The incoming line packets must merge to form one frame packet. If you transmit a single pixel per clock cycle, bit 0 of the incoming tuser signal marks the first pixel of each frame. The IP concatenates packets until bit 0 of tuser is asserted. If the number of pixels per line is not a multiple of the pixels per clock, the extra pixels in the final clock cycle of data are effectively empty and you must ignore them. You must specify the width of the incoming video frame via the register map. The IP uses this width information to determine which (if any) pixels it should ignore at the end of each line when concatenating the packets.

  2. Adds the frame packet header and the control packet

    Avalon Streaming Video requires that each frame packet begins with a one cycle header specifying a packet type of 0. The IP adds this header to the frame packet created previously. Avalon Streaming Video also recommends that each frame packet is preceded by a control packet (of type-15) that specifies the width, height, and interlacing scheme of the following frame. You supply the width and height via the register map, as the initial value for interlacing specifier. The IP uses these values to control Avalon Streaming control packets that it adds to the stream. If you select an interlacing specifier for progressive video, the IP uses this value for all control packets. If the interlacing specifier identifies an interlaced scheme, the IP toggles the f0/f1 bit automatically in the outgoing control packets.

  3. Converts Avalon Streaming ready latency 0 to 1

    The IP replaces the AXI4-Stream tlast signal with the Avalon Streaming startofpacket and endofpacket signals. The IP creates the empty signal (if the number of pixels per clock cycle is greater than 1). The IP reformats the AXI4-Stream byte aligned tdata to non-byte aligned Avalon Streaming data. The interface is now compliant with the Avalon Streaming protocol, but with a ready latency of 0. Avalon Streaming Video requires that the ready latency is 1, so the IP converts the ready latency from 0 to 1.

Intel FPGA streaming video full to Avalon streaming video

Converting Intel FPGA streaming video full to Avalon streaming video is similar to converting from Intel FPGA streaming video lite. Steps 1 and 3 are the same, but step 2 is different because the Intel FPGA streaming video full supports nonvideo packets.

You can extract the information required to populate the Avalon streaming video control packet from the image info packet in the Intel FPGA streaming video stream. The Avalon memory-mapped control agent interface is not required.

All Intel FPGA streaming video nonvideo packets with a type in the range 0-15 have specified or reserved functions and cannot be translated to Avalon streaming video. The IP removes these packets from the stream regardless of the value you select for the How Intel FPGA Streaming Video aux packets are handled parameter. If you select Discard all user packets received, the IP discards all user-defined auxiliary control packets received from the Intel FPGA Streaming video input. If you select Discard all user packets received, the optional auxiliary streaming input interface turns on. The IP discards any packets received from this interface, as this interface can carry associated payloads for auxiliary control packets.

If you select the option to pass through auxiliary packets, the IP must discard in-band packets with types 0-15 as these do not translate to Avalon streaming video. The IP must discard types 16, 28 and 31 as they map to reserved types in Avalon streaming video. For the remaining packet types, the IP looks at the value of the flag in bit 5 of the first data beat indicating if a packet on the auxiliary interface accompanies the packet. If the flag is not set, the IP creates an output packet containing just the header beat with the packet type minus 16. If the flag is set, the IP propagates a packet from the auxiliary interface to the output, with a single beat header appended to the front containing the in-band packet type minus 16. This process is the reverse of propagating user packets when converting from Avalon streaming video to Intel FPGA streaming video full.

The in-band packets that indicate a packet exists on the auxiliary interface may have between 1 and 4 beats of data. However, the IP only reads the data in the first beat, as it ignores all other data in the conversion process. The auxiliary interface conforms to the Intel FPGA streaming video protocol and can carry all packet types. The IP discards all image information, end of field, and all auxiliary control packets. The IP forwards all other packets, as these are data packets for any auxiliary control packets received on the main Intel FPGA Streaming video input.

Intel FPGA streaming video full allows auxiliary control packets to arrive in the stream both before the field data (the line packets), and between the final lines packet and the end of frame packet (both before and after the field). Avalon streaming video only allows user packets before the field packet. The IP considers any packets after the field as part of the next field. If the IP encounters auxiliary control packets after the field in Intel FPGA streaming video full, it still converts them to Avalon streaming video, but considers them part of the following frame. You should avoid the use of auxiliary control packets with types 17-31 after the field if this behavior is not acceptable.

Intel FPGA streaming video lite to Intel FPGA streaming video full

Converting from the lite variant to the full variant of Intel FPGA streaming video is a light-weight process because both variants use the same data format and packetization to transmit lines of video. You must add an image information packet before the first line of each field, and an end-of-field packet after the final line. The IP takes the information required to populate the image information packet from the register map. The broken field flag is the only information required for the end-of-field packet. The broken flag is set if the number of lines received for the given frame does not match the field height set in the register map and the field count. The field count is set from a counter that you can reset to zero via the register map at any time, and which increments at the end of each field.

Intel FPGA streaming video full to Intel FPGA streaming video lite

When converting from the full variant to the lite variant of Intel FPGA streaming video both variants use the same data format and packetization to transmit lines of video. To convert, the IP removes any image information, end of field, or auxiliary control packets (marked by asserting bit 1 of tuser for the first beat of the packet) from the input stream.

Pixel data format

The pixel data format for Avalon Streaming Video and Intel FPGA Streaming Video is almost identical. Intel FPGA Streaming Video requires that the width of each pixel is rounded up to the next whole number of bytes. Any extra bits required can be filled with zeros, ones, or any random data. Avalon Streaming Video has no such requirement and uses only the required bits for each pixel. The Protocol Converter adds the required extra bits when converting from Avalon Streaming Video to Intel FPGA Streaming Video. It removes them when converting from Intel FPGA Streaming Video to Avalon Streaming Video.

Avalon Streaming Video and Intel FPGA Streaming Video both specify how the color planes in each pixel should be arranged for RGB and YCbCr formatted data. For YCbCr data, the protocols specify the color plane ordering for 4:4:4, 4:2:2 and 4:2:0 chroma sampling. The color plane ordering is almost identical between the two protocols, apart from swapping Y and Cr planes in the case of YCbCr 4:4:4. The Protocol Converter IP can implement the swap, but you must specify the color space and chroma sampling for each frame. You can specify either via the parameters or the register map accessed through an Avalon memory-mapped agent interface.

You can turn on or turn off the Avalon memory-mapped agent interface via a parameter. If the Avalon memory-mapped agent interface is turned on, specify the color space and chroma sampling at run time via the register map. If the Avalon memory-mapped agent interface is not turned on, specify the color space and chroma sampling in the Video color space and Video chroma sampling parameters respectively.

If the Protocol Convert IP converts from Intel FPGA Streaming Video to Avalon Streaming Video, turn on the Avalon memory-mapped agent interface and do not use the parameters. If the Protocol Convert IP converts from Avalon Streaming Video to Intel FPGA Streaming Video, the Avalon memory-mapped agent interface is optional. If you know the color space and chroma sampling are fixed for the system, you can opt to turn off the agent interface and specify the color space and chroma sampling via the parameters. If the color space and chroma sampling may vary at run time, turn on the agent interface and specify the values in the register map.

For conversions both ways, the IP gates the color plane swap for YCbCr 4:4:4 formatted data by the YCbCr 444 color swap parameter. You must turn on this option for the IP to apply the color plane swap.

4:2:0 chroma sampled video

Avalon streaming video requires you to declare a fixed number of color planes per pixel. The packing of 4:2:0 color planes does not fully align with this definition of a pixel. 4 luma samples exist for every pair of Cb and Cr samples, so the effective number of color planes per pixel is 1.5 (1 luma sample and ½ a chroma sample). You cannot configure Avalon streaming video to have 1.5 colors per pixel, so the IP packs two luma samples with each chroma to make an atom of transport on the Avalon streaming video interface. The Avalon streaming video protocol considers this group of three color planes to be a pixel, even though it contains 2 luma samples and is effectively 2 pixels. The width value reported in the control packet counts the number of 3 color plane groups that interface treats as a pixel, so the width value reported is always half the actual field width for 4:2:0 sampled data.

Both variants of Intel FPGA streaming video protocol pack two luma samples into an atom of transport that you consider a pixel in 4:4:4 or 4:2:2 sampling. The protocol similarly defines chroma sampling. The field width specified in the image information packets (when using the full variant of Intel FPGA streaming video) and the register map is always the true field width.

The protocol converter IP requires you to specify the chroma sampling and automatically doubles or halves the reported widths where required.

End of field detection in Intel FPGA streaming video lite

For Avalon Streaming Video, the endofpacket signal marks the end of each video frame that is asserted on the final pixel of the video data packet.

In Avalon Streaming Video, you cannot transmit the final pixel of each frame until you are certain that it is the final pixel, otherwise you risk driving the endofpacket signal incorrectly.

For Intel FPGA Streaming Video the end of each frame is inferred by receiving the start-of-frame marker for the next frame, which is explicitly indicated in the protocol. You might see potential latency issues when converting from Intel FPGA Streaming Video to Avalon Streaming Video. The IP cannot transmit the final pixel of each frame at the output until it receives the first pixel of the next frame at the input. When converting to Intel FPGA streaming video full, the IP cannot send the EOF packet for a given frame until it sees the first pixel of the next frame.

If the video application has no significant blanking (delay) between the last pixel of one frame and the first pixel of the next frame, the IP gives little or no delay in sending out the final pixel of each frame (Avalon streaming video) or end of frame packet (Intel FPGA streaming video full). If the application does have significant blanking, the delay to transmit the final pixel or end of frame may be too long. The Protocol Converter IP includes an option to remove this delay.

If you turn on Low latency mode, the Protocol Converter IP transmits the Avalon Streaming Video frame endofpacket or Intel FPGA streaming video full EOF packet according to the number of lines it expects in each frame, as you specify in the register map. The Intel FPGA Streaming Video protocol transmits each line of video data as a packet, so the IP terminates the output frame at the end of the input packet for the specified number of lines. If the IP receives any additional lines, the IP discards them and does not transmit them at the output.

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