Video and Vision Processing Suite Intel® FPGA IP User Guide

Download PDF
ID 683329
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel® FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Text Box Intel® FPGA IP 43. Tone Mapping Operator Intel® FPGA IP 44. Test Pattern Generator Intel® FPGA IP 45. Unsharp Mask Intel® FPGA IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer Intel® FPGA IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO Intel® FPGA IP 51. Video Timing Generator Intel® FPGA IP 52. Vignette Correction Intel® FPGA IP 53. Warp Intel® FPGA IP 54. White Balance Correction Intel® FPGA IP 55. White Balance Statistics Intel® FPGA IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. Adaptive Noise Reduction Intel® FPGA IP x
10.1. About the Adaptive Noise Reduction IP 10.2. Adaptive Noise Reduction IP Parameters 10.3. Adaptive Noise Reduction IP Functional Description 10.4. Adaptive Noise Reduction IP Registers 10.5. Adaptive Noise Reduction IP Software API
10.1. About the Adaptive Noise Reduction IP x
10.1.1. Adaptive Noise Reduction IP Performance and Resources
10.3. Adaptive Noise Reduction IP Functional Description x
10.3.1. Adaptive Noise Reduction IP Interfaces
11. Advanced Test Pattern Generator Intel® FPGA IP x
11.1. About the Advanced Test Pattern Generator IP 11.2. Advanced Test Pattern Generator IP Parameters 11.3. Advanced Test Pattern Generator IP Functional Description 11.4. Advanced Test Pattern Generator IP Registers 11.5. Advanced Test Pattern Generator IP Software API
11.1. About the Advanced Test Pattern Generator IP x
11.1.1. Advanced Test Pattern Generator IP Performance and Resources
11.3. Advanced Test Pattern Generator IP Functional Description x
11.3.1. Test Patterns 11.3.2. Dimensions, Offsets, and Alpha Settings 11.3.3. Run-time Settings 11.3.4. Advanced Test Pattern Generator IP Interfaces
12. AXI-Stream Broadcaster Intel® FPGA IP x
12.1. About the AXI-Stream Broadcaster IP 12.2. AXI-Stream Broadcaster IP Parameters 12.3. AXI-Stream Broadcaster IP Interfaces
12.1. About the AXI-Stream Broadcaster IP x
12.1.1. AXI-Stream Broadcaster IP Features 12.1.2. AXI-Stream Broadcaster IP Performance and Resources
13. Bits per Color Sample Adapter Intel® FPGA IP x
13.1. About the Bits per Color Sample Adapter IP 13.2. Bits per Color Sample Adapter IP Parameters 13.3. Bits per Color Sample Adapter IP Dithering Functional Description 13.4. Bits per Color Sample Adapter IP Registers 13.5. Bits per Color Sample Adapter Software API
13.1. About the Bits per Color Sample Adapter IP x
13.1.1. Bits per Color Sample Adapter IP Performance and Resources
13.3. Bits per Color Sample Adapter IP Dithering Functional Description x
13.3.1. Bits per Color Sample Adapter IP Interfaces
14. Black Level Correction Intel® FPGA IP x
14.1. About the Black Level Correction IP 14.2. Black Level Correction IP Parameters 14.3. Black Level Correction IP Functional Description 14.4. Black Level Correction IP Registers 14.5. Black Level Correction IP Software API
14.1. About the Black Level Correction IP x
14.1.1. Black Level Correction IP Performance and Resources
14.3. Black Level Correction IP Functional Description x
14.3.1. Black Level Correction IP Interfaces
15. Black Level Statistics Intel® FPGA IP x
15.1. About the Black Level Statistics IP 15.2. Black Level Statistics IP Parameters 15.3. Black Level Statistics IP Interfaces 15.4. Black Level Statistics IP Registers 15.5. Black Level Statistics IP Software API
15.1. About the Black Level Statistics IP x
15.1.1. Black Level Statistics IP Performance and Resources
16. Chroma Key Intel® FPGA IP x
16.1. About the Chroma Key IP 16.2. Chroma Key IP Parameters 16.3. Chroma Key IP Interfaces 16.4. Chroma Key Replacement 16.5. Chroma Key IP Registers 16.6. Chroma Key IP Software API
16.1. About the Chroma Key IP x
16.1.1. Chroma Key IP Performance and Resources
17. Chroma Resampler Intel® FPGA IP x
17.1. About the Chroma Resampler IP 17.2. Chroma Resampler IP Parameters 17.3. Chroma Resampler IP Functional Description 17.4. Chroma Resampler IP Registers 17.5. Chroma Resampler IP Software API
17.1. About the Chroma Resampler IP x
17.1.1. Chroma Resampler Performance and Resources
17.3. Chroma Resampler IP Functional Description x
17.3.1. Chroma Resampler IP Interfaces
18. Clipper Intel® FPGA IP x
18.1. About the Clipper IP 18.2. Clipper IP Parameters 18.3. Clipper IP Interfaces 18.4. Clipper IP Registers 18.5. Clipper IP Software API
18.1. About the Clipper IP x
18.1.1. Clipper IP Performance and Resources
19. Clocked Video Input Intel® FPGA IP x
19.1. About the Clocked Video Input IP 19.2. Initializing the Clocked Video Input IP 19.3. Clocked Video Input IP Parameters 19.4. Clocked Video Input IP Interfaces 19.5. Clocked Video Input IP Registers 19.6. Clocked Video Input IP Software API
19.1. About the Clocked Video Input IP x
19.1.1. Clocked Video Input IP Features 19.1.2. Clocked Video Input IP Performance and Resources
20. Clocked Video to Full-Raster Converter Intel® FPGA IP x
20.1. About the Clocked Video to Full-Raster Converter IP 20.2. Clocked Video to Full-Raster Converter Parameters 20.3. Clocked Video to Full-Raster Converter Block Description 20.4. Clocked Video Converter to Full-Raster IP Registers
20.1. About the Clocked Video to Full-Raster Converter IP x
20.1.1. Clocked Video to Full-Raster Converter Features 20.1.2. Clocked Video to Full-Raster Converter Performance and Resources
20.3. Clocked Video to Full-Raster Converter Block Description x
20.3.1. Clocked Video to Full-Raster Converter Interfaces
21. Clocked Video Output Intel® FPGA IP x
21.1. About the Clocked Video Output IP 21.2. Clocked Video Output IP Parameters 21.3. Clocked Video Output IP Functional Description 21.4. Clocked Video Output IP Interfaces 21.5. Clocked Video Output IP Registers 21.6. Clocked Video Output IP Software API
21.1. About the Clocked Video Output IP x
21.1.1. Clocked Video Output IP Performance and Resources 21.1.2. Clocked Video Output IP Features
22. Color Plane Manager Intel® FPGA IP x
22.1. About the Color Plane Manager IP 22.2. Color Plane Manager IP Parameters 22.3. Color Plane Manager IP Functional Description 22.4. Color Plane Manager IP Registers 22.5. Color Plane Manager Software API
22.1. About the Color Plane Manager IP x
22.1.1. Color Plane Manager IP Performance and Resources
22.3. Color Plane Manager IP Functional Description x
22.3.1. Color Plane Manager IP Interfaces
23. Color Space Converter Intel® FPGA IP x
23.1. About the Color Space Converter IP 23.2. Color Space Converter IP Parameters 23.3. Color Space Converter IP Functional Description 23.4. Color Space Converter IP Registers 23.5. Color Space Converter IP Software API
23.1. About the Color Space Converter IP x
23.1.1. Color Space Converter IP Features 23.1.2. Color Space Converter IP Performance and Resources
23.3. Color Space Converter IP Functional Description x
23.3.1. Color Space Converter IP Interfaces
24. Defective Pixel Correction Intel® FPGA IP x
24.1. About the Defective Pixel Correction IP 24.2. Defective Pixel Correction IP Parameters 24.3. Defective Pixel Correction IP Functional Description 24.4. Defective Pixel Correction IP Registers 24.5. Defective Pixel Correction IP Software API
24.1. About the Defective Pixel Correction IP x
24.1.1. Defective Pixel Correction IP Performance and Resources
24.3. Defective Pixel Correction IP Functional Description x
24.3.1. Defective Pixel Correction IP Interfaces
25. Deinterlacer Intel® FPGA IP x
25.1. About the Deinterlacer IP 25.2. Deinterlacer Parameters 25.3. Deinterlacer IP Functional Description 25.4. Deinterlacer IP Registers 25.5. Deinterlacer IP Software API
25.1. About the Deinterlacer IP x
25.1.1. Deinterlacer Performance and Resources
25.3. Deinterlacer IP Functional Description x
25.3.1. Deinterlacer Interfaces
26. Demosaic Intel® FPGA IP x
26.1. About the Demosaic IP 26.2. Demosaic IP Parameters 26.3. Demosaic IP Functional Description 26.4. Demosaic IP Registers 26.5. Demosaic IP Software API
26.1. About the Demosaic IP x
26.1.1. Demosaic IP Performance and Resources
26.3. Demosaic IP Functional Description x
26.3.1. Demosaic IP Interfaces
27. FIR Filter Intel® FPGA IP x
27.1. About the FIR Filter 27.2. FIR Filter Parameters 27.3. FIR Filter IP Operation 27.4. FIR Filter Interfaces 27.5. FIR Filter Registers 27.6. FIR Filter IP Software API
27.1. About the FIR Filter x
27.1.1. FIR Filter IP Performance and Resources
27.3. FIR Filter IP Operation x
27.3.1. FIR Filter Processing 27.3.2. FIR Filter Precision 27.3.3. FIR Coefficient Specification 27.3.4. FIR Filter Symmetry 27.3.5. Result to Output Data Type Conversion
27.3.4. FIR Filter Symmetry x
27.3.4.1. No Symmetry 27.3.4.2. Horizontal Symmetry 27.3.4.3. Vertical Symmetry 27.3.4.4. Horizontal and Vertical Symmetry 27.3.4.5. Diagonal Symmetry
28. Frame Cleaner Intel® FPGA IP x
28.1. About the Frame Cleaner IP 28.2. Frame Cleaner IP Parameters 28.3. Frame Cleaner IP Functional Description 28.4. Frame Cleaner IP Interfaces 28.5. Frame Cleaner IP Registers 28.6. Frame Cleaner IP Software API
28.1. About the Frame Cleaner IP x
28.1.1. Frame Cleaner IP Performance and Resources
29. Full-Raster to Clocked Video Converter Intel® FPGA IP x
29.1. About the Full-Raster to Clocked Video Converter 29.2. Full Raster to Clocked Video Converter Parameters 29.3. Full-Raster to Clocked Video Converter Block Description 29.4. Full-Raster to Clocked Video Converter Registers
29.1. About the Full-Raster to Clocked Video Converter x
29.1.1. Full-Raster to Clocked Video Converter Features 29.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
29.3. Full-Raster to Clocked Video Converter Block Description x
29.3.1. Full Raster to Clocked Video Converter Interfaces
30. Full-Raster to Streaming Converter Intel® FPGA IP x
30.1. About the Full-Raster to Streaming Converter IP 30.2. Full-Raster to Streaming Converter Parameters 30.3. Full-Raster to Streaming Converter Block Description
30.1. About the Full-Raster to Streaming Converter IP x
30.1.1. Full-Raster to Streaming Converter Features 30.1.2. Full-Raster to Streaming Converter Performance and Resources
30.3. Full-Raster to Streaming Converter Block Description x
30.3.1. Full-Raster to Streaming Converter Interfaces
31. Genlock Controller Intel® FPGA IP x
31.1. About the Genlock Controller IP 31.2. Genlock Controller IP Parameters 31.3. Genlock Controller IP Functional Description 31.4. Using Genlock Controller IP Software 31.5. Genlock Controller IP Registers 31.6. Genlock Controller IP Software API
31.1. About the Genlock Controller IP x
31.1.1. Genlock Controller IP Performance and Resources
31.3. Genlock Controller IP Functional Description x
31.3.1. Genlock Controller IP Interfaces
31.4. Using Genlock Controller IP Software x
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 31.4.3. Setting the VCXO hold over 31.4.4. Restarting the Genlock Controller IP 31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 31.4.7. Disturbing a Reference Clock (a cable pull)
32. Generic Crosspoint Intel® FPGA IP x
32.1. About the Generic Crosspoint IP 32.2. Generic Crosspoint IP Parameters 32.3. Generic Crosspoint IP Interfaces 32.4. Generic Crosspoint IP Registers 32.5. Generic Crosspoint IP Software API
32.1. About the Generic Crosspoint IP x
32.1.1. Generic Crosspoint IP Features 32.1.2. Generic Crosspoint Performance and Resources
33. Genlock Signal Router Intel® FPGA IP x
33.1. About the Genlock Signal Router IP 33.2. Genlock Signal Router IP Parameters 33.3. Genlock Signal Router IP Interfaces 33.4. Genlock Signal Router IP Registers 33.5. Genlock Signal Router IP Software API
33.1. About the Genlock Signal Router IP x
33.1.1. Genlock Signal Router IP Features 33.1.2. Genlock Signal Router IP Performance and Resources
34. Guard Bands Intel® FPGA IP x
34.1. About the Guard Bands IP 34.2. Guard Bands IP Parameters 34.3. Guard Bands IP Interfaces 34.4. Guard Bands IP Registers 34.5. Guard Bands IP Software API
34.1. About the Guard Bands IP x
34.1.1. Guard Bands IP Performance and Resources
35. Histogram Statistics Intel® FPGA IP x
35.1. About the Histogram Statistics IP 35.2. Histogram Statistics IP Parameters 35.3. Histogram Statistics IP Interfaces 35.4. Histogram Statistics IP Registers 35.5. Histogram Statistics IP Software API
35.1. About the Histogram Statistics IP x
35.1.1. Histogram Statistics IP Performance and Resources
36. Interlacer Intel® FPGA IP x
36.1. About the Interlacer IP 36.2. Interlacer IP Parameters 36.3. Interlacer IP Functional Description 36.4. Interlacer IP Registers 36.5. Interlacer IP Software API
36.1. About the Interlacer IP x
36.1.1. Interlacer IP Performance and Resources
36.3. Interlacer IP Functional Description x
36.3.1. Interlacer IP Interfaces
37. Mixer Intel® FPGA IP x
37.1. About the Mixer IP 37.2. Mixer IP Parameters 37.3. Mixer IP Functional Description 37.4. Mixer IP Registers 37.5. Mixer IP Software API
37.1. About the Mixer IP x
37.1.1. Mixer IP Performance and Resources
37.3. Mixer IP Functional Description x
37.3.1. Mixer IP Interfaces
38. Pixels in Parallel Converter Intel® FPGA IP x
38.1. About the Pixels in Parallel Converter IP 38.2. Pixels in Parallel Converter IP Parameters 38.3. Pixels in Parallel Converter Interfaces 38.4. Pixels in Parallel Converter Registers 38.5. Pixels in Parallel Converter IP Software API
38.1. About the Pixels in Parallel Converter IP x
38.1.1. Pixels in Parallel Converter IP Performance and Resources
39. Scaler Intel® FPGA IP x
39.1. About the Scaler 39.2. Scaler IP Parameters 39.3. Scaler IP Functional Description 39.4. Scaler IP Registers 39.5. Scaler IP Software API
39.1. About the Scaler x
39.1.1. Scaler IP Performance and Resources
39.2. Scaler IP Parameters x
39.2.1. Scaler Maximum Resolution
39.3. Scaler IP Functional Description x
39.3.1. Coefficient Selection 39.3.2. Coefficient Quantization 39.3.3. Filter Behavior at Edge Boundaries 39.3.4. Partial Frame Scaling 39.3.5. 422 and 420 Chroma Sampled Data Scaling 39.3.6. Scaler IP Interfaces
39.3.1. Coefficient Selection x
39.3.1.1. Updating Scaler IP Runtime Coefficients
40. Stream Cleaner Intel® FPGA IP x
40.1. About the Stream Cleaner IP 40.2. Stream Cleaner IP Parameters 40.3. Stream Cleaner IP Functional Description
40.1. About the Stream Cleaner IP x
40.1.1. Stream Cleaner IP Performance and Resources
40.3. Stream Cleaner IP Functional Description x
40.3.1. Stream Cleaner IP Interfaces
41. Switch Intel® FPGA IP x
41.1. About the Switch IP 41.2. Switch IP Parameters 41.3. Switch IP Functional Description 41.4. Switch IP Registers 41.5. Switch IP Software API
41.1. About the Switch IP x
41.1.1. Switch IP Performance and Resources
41.3. Switch IP Functional Description x
41.3.1. Switch IP Latency 41.3.2. Switch IP Interfaces
42. Text Box Intel® FPGA IP x
42.1. About the Text Box IP 42.2. Text Box IP Parameters 42.3. Text Box IP Functional Description 42.4. Text Box IP Registers 42.5. Text Box IP Software API
42.1. About the Text Box IP x
42.1.1. Text Box IP Performance and Resources
42.3. Text Box IP Functional Description x
42.3.1. Writing Text at Run Time with Double Buffering 42.3.2. Writing Text at Run Time without Double Buffering 42.3.3. Text Box IP Interfaces
43. Tone Mapping Operator Intel® FPGA IP x
43.1. About the Tone Mapping Operator IP 43.2. TMO IP Parameters 43.3. TMO IP Block Description 43.4. TMO IP Registers 43.5. TMO IP Software API
43.1. About the Tone Mapping Operator IP x
43.1.1. TMO IP Features 43.1.2. TMO IP Performance and Resource Utilization
43.3. TMO IP Block Description x
43.3.1. TMO IP Interfaces 43.3.2. TMO IP Latency
44. Test Pattern Generator Intel® FPGA IP x
44.1. About the Test Pattern Generator IP 44.2. Test Pattern Generator IP Parameters 44.3. Test Pattern Generator IP Functional Description 44.4. Test Pattern Generator IP Registers 44.5. Test Pattern Generator IP Software API
44.1. About the Test Pattern Generator IP x
44.1.1. Test Pattern Generator IP Performance and Resources
44.3. Test Pattern Generator IP Functional Description x
44.3.1. Test Patterns 44.3.2. Output Subsampling and Color Space 44.3.3. Run-time Settings 44.3.4. Test Pattern Generator IP Interfaces
45. Unsharp Mask Intel® FPGA IP x
45.1. About the Unsharp Mask IP 45.2. Unsharp Mask IP Parameters 45.3. Unsharp Mask IP Functional Description 45.4. Unsharp Mask IP Registers 45.5. Unsharp Mask IP Software API
45.1. About the Unsharp Mask IP x
45.1.1. Unsharp Mask IP Performance and Resources
45.3. Unsharp Mask IP Functional Description x
45.3.1. Unsharp Mask IP Interfaces
46. Video and Vision Monitor Intel FPGA IP x
46.1. About the Video and Vision Monitor IP 46.2. Video and Vision Monitor IP Parameters 46.3. Video and Vision Monitor IP Functional Description 46.4. Video and Vision Monitor IP Registers 46.5. Video and Vision Monitor Software API
46.1. About the Video and Vision Monitor IP x
46.1.1. Video and Vision Monitor IP Performance and Resources
46.3. Video and Vision Monitor IP Functional Description x
46.3.1. Video and Vision Monitor IP Interfaces
47. Video Frame Buffer Intel® FPGA IP x
47.1. About the Video Frame Buffer IP 47.2. Video Frame Buffer IP Parameters 47.3. Video Frame Buffer IP Functional Description 47.4. Video Frame Buffer IP Registers 47.5. Video Frame Buffer IP Software API
47.1. About the Video Frame Buffer IP x
47.1.1. Video Frame Buffer Performance and Resources
47.3. Video Frame Buffer IP Functional Description x
47.3.1. Video Frame Buffer IP Interfaces
48. Video Frame Reader Intel FPGA IP x
48.1. About the Video Frame Reader IP 48.2. Video Frame Reader IP Parameters 48.3. Video Frame Reader IP Functional Description 48.4. Video Frame Reader IP Registers 48.5. Video Frame Reader IP Software API
48.1. About the Video Frame Reader IP x
48.1.1. Video Frame Reader IP Performance and Resources
48.3. Video Frame Reader IP Functional Description x
48.3.1. Video Frame Reader IP Interfaces
49. Video Frame Writer Intel FPGA IP x
49.1. About the Video Buffer Writer IP 49.2. Video Frame Writer IP Parameters 49.3. Video Frame Writer IP Functional Description 49.4. Video Frame Writer IP Registers 49.5. Video Frame Writer IP Software API
49.1. About the Video Buffer Writer IP x
49.1.1. Video Frame Writer IP Performance and Resources
49.3. Video Frame Writer IP Functional Description x
49.3.1. Video Frame Writer IP Interfaces
50. Video Streaming FIFO Intel® FPGA IP x
50.1. About the Video Streaming FIFO IP 50.2. Video Streaming FIFO IP Parameters 50.3. Video Streaming FIFO IP Interfaces
50.1. About the Video Streaming FIFO IP x
50.1.1. Video Streaming FIFO IP Performance and Resources
51. Video Timing Generator Intel® FPGA IP x
51.1. About the Video Timing Generator IP 51.2. Video Timing Generator IP Parameters 51.3. Video Timing Generator IP Functional Description 51.4. Video Timing Generator IP Interfaces 51.5. Video Timing Generator IP Registers 51.6. Video Timing Generator IP Software API
51.1. About the Video Timing Generator IP x
51.1.1. Video Timing Generator IP Features 51.1.2. Video Timing Generator IP Performance and Resources
52. Vignette Correction Intel® FPGA IP x
52.1. About the Vignette Correction IP 52.2. Vignette Correction IP Parameters 52.3. Vignette Correction IP Interfaces 52.4. Vignette Correction IP Registers 52.5. Vignette Correction IP Software API
52.1. About the Vignette Correction IP x
52.1.1. Vignette Correction IP Performance and Resources
53. Warp Intel® FPGA IP x
53.1. About the Warp IP 53.2. Warp IP Parameters 53.3. Warp IP Block Description 53.4. Warp IP Registers 53.5. Warp IP Software API
53.1. About the Warp IP x
53.1.1. Warp IP Features 53.1.2. Warp IP Performance and Resource Utilization
53.3. Warp IP Block Description x
53.3.1. Block Cache Tool 53.3.2. Warp IP Interfaces 53.3.3. Warp IP Latency 53.3.4. External Memory for Warp IP
53.5. Warp IP Software API x
intel_vvp_warp_driver intel_vvp_warp_init_instance intel_vvp_warp_create_channel intel_vvp_warp_create_double_channel intel_vvp_warp_create_quad_channel intel_vvp_warp_create_easy_warp_channel intel_vvp_warp_add_engine_to_channel intel_vvp_warp_free_channel intel_vvp_warp_configure_channel intel_vvp_warp_apply_transform intel_vvp_warp_bypass intel_vvp_warp_reset_skip_ram intel_vvp_warp_reset_input_skip_ram intel_vvp_warp_check_easy_warp_capable intel_vvp_warp_set_easy_warp intel_vvp_warp_set_output_latency intel_vvp_warp_get_channel_framebuffer_size intel_vvp_warp_get_debug_register intel_vvp_warp_get_input_debug_register intel_vvp_warp_get_output_debug_register intel_vvp_warp_get_engine_debug_register intel_vvp_warp_get_engine_status intel_vvp_warp_get_output_status Data structures and types intel_vvp_warp_base_t intel_vvp_warp_instance intel_vvp_warp_channel intel_vvp_warp_channel_config intel_vvp_warp_data intel_vvp_warp_engine_data WarpDataGenerator GenerateData GenerateLatencyParams GetLastErrorCode GetErrorString WarpMesh mesh_node_t WarpMeshPtr WarpDataContext WarpData WarpEngineData mesh_entry_t, filter_entry_t, fetch_entry_t WarpLatencyParams Helper functions GetHwContext GenerateDriverData intel_vvp_warp_mesh WarpConfigurator SetInputResolution, GetInputResolution, SetOutputResolution, GetOutputResolution GenerateMeshFromFixed, GenerateMeshFromCorners, GenerateMeshFromArbitrary SetHSize, GetHSize, SetVSize, GetVSize SetHOffset, GetHOffset, SetVOffset, GetVOffset SetRotate, GetRotate SetHMirror, GetHMirror, SetVMirror, GetVMirror SetZoom, GetZoom SetHKeystone, GetHKeystone, SetVKeystone, GetVKeystone SetFOV, GetFOV SetVAxisOffset, GetVAxisOffset SetPreRadial, GetPreRadial SetCorner, GetCorner SetCornerNorm, GetCornerNorm SetArbitraryKnotsNum, GetArbitraryKnotsNum SetArbitraryKnot, GetArbitraryKnot SetArbitraryKnotNorm, GetArbitraryKnotNorm SetMaintainRatio, GetMaintainRatio SetShrinkToFit, GetShrinkToFit ECornerId 53.5.1. Using Warp IP Software 53.5.2. Warp IP Software Code Examples
54. White Balance Correction Intel® FPGA IP x
54.1. About the White Balance Correction IP 54.2. White Balance Correction IP Parameters 54.3. White Balance Correction IP Functional Description 54.4. White Balance Correction IP Registers 54.5. White Balance Correction IP Software API
54.1. About the White Balance Correction IP x
54.1.1. White Balance Correction IP Performance and Resources
54.3. White Balance Correction IP Functional Description x
54.3.1. White Balance Correction IP Interfaces
55. White Balance Statistics Intel® FPGA IP x
55.1. About the White Balance Statistics IP 55.2. White Balance Statistics IP Parameters 55.3. White Balance Statistics IP Interfaces 55.4. White Balance Statistics IP Registers 55.5. White Balance Statistics IP Software API
55.1. About the White Balance Statistics IP x
55.1.1. White Balance Statistics IP Performance and Resources
56. Design Security x
56.1. Memory Subsystems 56.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel® FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Text Box Intel® FPGA IP
43. Tone Mapping Operator Intel® FPGA IP
44. Test Pattern Generator Intel® FPGA IP
45. Unsharp Mask Intel® FPGA IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer Intel® FPGA IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO Intel® FPGA IP
51. Video Timing Generator Intel® FPGA IP
52. Vignette Correction Intel® FPGA IP
53. Warp Intel® FPGA IP
54. White Balance Correction Intel® FPGA IP
55. White Balance Statistics Intel® FPGA IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide

53.5. Warp IP Software API

The Warp IP software is implemented in C and C++. This topic describes the API functions in the code and provides code examples.
Figure 161. Warp software architecture

The software includes:

  • intel_vvp_warp_driver
  • intel_vvp_warp_data
  • intel_vvp_warp_mesh

The intel_vvp_warp_driver is the warp IP driver. It provides API for initializing, configuring, and controlling the Warp IP, warp video channel management, and using debug features.

The intel_vvp_warp_data is the software component that generates mesh, cache, and filter coefficient data required by the warp IP. Place generated data in a region of RAM accessed by the warp IP. This location and other necessary parameters are passed to the warp driver.

This component requires transformation mesh in a predefined format as the main input data. It also requires some IP parameters e.g. number of available engines, processing block dimensions, block cache size, single memory bounce setting.

The intel_vvp_warp_mesh is the software component that generates warp meshes for common affine transformations such as translation, rotation, zoom; perspective transformations e.g. keystone and radial distortion (fisheye) and arbitrary warps defined by a set of curves. Meshes are generated in the format required by the intel_vvp_warp_data interface.

You can use this reference software in a number of real-world applications. However, in some more complex cases you might want to use external software to generate transformation mesh. For example, when projecting image onto a complex surface.

You can deploy the software on a Nios V based system. However, because of computational intensity of the mesh and data generating components, Intel recommends an SoC with a dedicated CPU such as an Intel Arria 10 SX device.

intel_vvp_warp_driver

Table 1145.   intel_vvp_warp_driver API reference

The software driver for Warp IP provides the following set of API functions.
Name Description
intel_vvp_warp_init_instance Initialize driver instance
intel_vvp_warp_create_channel Create single engine video processing channel
intel_vvp_warp_create_double_channel Create dual engine video processing channel
intel_vvp_warp_create_quad_channel Create quad engine video processing channel
intel_vvp_warp_create_easy_warp_channel Create easy warp video processing channel
intel_vvp_warp_add_engine_to_channel Add a warp engine to existing channel
intel_vvp_warp_free_channel Free video processing channel
intel_vvp_warp_configure_channel Configure video processing channel
intel_vvp_warp_apply_transform Apply video transformation
intel_vvp_warp_bypass Bypass video processing
intel_vvp_warp_reset_skip_ram Reset skip RAM page
intel_vvp_warp_reset_input_skip_ram Reset input skip RAM page
intel_vvp_warp_check_easy_warp_capable Check if a warp channel can perform Easy warp
intel_vvp_warp_set_easy_warp Set easy warp transformation
intel_vvp_warp_set_output_latency Set warp output latency
intel_vvp_warp_get_channel_framebuffer_size Get total size of the frame buffer RAM required
intel_vvp_warp_get_debug_register Get contents of a warp debug register
intel_vvp_warp_get_input_debug_register Get contents of a warp input debug register
intel_vvp_warp_get_output_debug_register Get contents of a warp output debug register
intel_vvp_warp_get_engine_debug_register Get contents of a warp engine debug register
intel_vvp_warp_get_engine_status Get current status flags of the warp engine
intel_vvp_warp_get_output_status Get current status flags of the warp output

intel_vvp_warp_init_instance 

int intel_vvp_warp_init_instance( intel_vvp_warp_instance_t* instance, intel_vvp_warp_base_t base)
Description
Initialize intel_vvp_warp driver instance
Arguments
instance – pointer to the intel_vvp_warp software driver instance structure
base – hardware access handler. In a bare metal environments such as Nios II it is defined as 32-bit unsigned integer representing physical address of the intel_vvp_warp IP on the CPU bus.
Return value
Zero on success, negative integer otherwise

intel_vvp_warp_create_channel intel_vvp_warp_create_double_channel intel_vvp_warp_create_quad_channel 

intel_vvp_warp_channel_t* intel_vvp_warp_create_channel(intel_vvp_warp_instance_t *instance, uint32_t input_idx, uint32_t engine_idx, uint32_t output_idx) intel_vvp_warp_channel_t* intel_vvp_warp_create_double_channel(intel_vvp_warp_instance_t *instance, uint32_t input_idx, uint32_t engine1_idx, uint32_t engine2_idx, uint32_t output_idx) intel_vvp_warp_create_quad_channel(intel_vvp_warp_instance_t
*instance, uint32_t input_idx, uint32_t output_idx)
Description
Create a video processing channel. The functions allocate hardware resources and initialize driver data structures necessary for processing a video stream up to 7680x4320 pixels.
Arguments

instance – pointer to initialized intel_vvp_warp_instance_t structure;

input_idx, engine_idx, engine2_idx, ouput_idx – indexes of the warp IP input, engines and output to use in this channel.

You can configure a single warp IP to provide multiple input, output, and processing engine blocks. These blocks are grouped into video processing channels arbitrarily by using index of the block.

The indexes must be in the range 0..num_inputs(num_outputs or num_engines respectively), where you can obtain num_inputs, num_outputs and num_engines through the intel_vvp_warp_instance_t structure after you initialize the driver instance.

Return value
Valid pointer to initialized intel_vvp_warp_channel_t structure on success, null pointer otherwise.

intel_vvp_warp_create_easy_warp_channel 

intel_vvp_warp_channel_t* intel_vvp_warp_create_easy_warp_channel(intel_vvp_warp_instance_t *instance, uint32_t input_idx, uint32_t output_idx)
Description
Create an easy warp video processing channel. The functions allocate hardware resources and initialize driver data structures necessary for processing a video stream up to 3840x2160 pixels using easy warp configuration.
Arguments

instance – pointer to initialized intel_vvp_warp_instance_t structure;

input_idx, ouput_idx – indexes of the warp IP input and output to use in this channel.

Return value
Valid pointer to initialized intel_vvp_warp_channel_t structure on success, null pointer otherwise.

intel_vvp_warp_add_engine_to_channel 

int intel_vvp_warp_add_engine_to_channel(intel_vvp_warp_channel_t* channel, uint32_t engine_idx)
Description

Add a warp engine to existing channel.

Warp IP allows you to split video processing between multiple engines. This function adds additional engines to already allocated channels and updates driver and channel data structures accordingly

Arguments

instance – pointer to the intel_vvp_warp software driver instance structure

engine_idx – indexes of the warp IP engine to add to the channel

Return value
Zero on success, negative integer otherwise

intel_vvp_warp_free_channel 

void intel_vvp_warp_free_channel(intel_vvp_warp_channel_t* channel)
Description
Delete video processing channel and release hardware resources and driver data structures allocated for it
Arguments
channel – a valid pointer to initialized intel_vvp_warp_channel_t structure
Return value
None

intel_vvp_warp_configure_channel 

int intel_vvp_warp_configure_channel(intel_vvp_warp_channel_t* channel, intel_vvp_warp_channel_config_t* cfg)
Description
Configure video processing channel data structures and allocated hardware by providing necessary parameters such as input/output resolutions, frame buffers location etc.
Arguments

channel – a valid pointer to initialized video processing channel;

cfg – a valid pointer to initialized intel_vvp_warp_channel_config_t structure.

Return value
Zero on success, negative integer otherwise

intel_vvp_warp_apply_transform 

int intel_vvp_warp_apply_transform(intel_vvp_warp_channel_t* channel, intel_vvp_warp_data_t* data)
Description
Start warping video by configuring the channel to use provided warp data coefficients
Arguments

channel – a valid pointer to initialized video processing channel

data – a valid pointer to initialized intel_vvp_warp_data_t structure.

Return value
Zero on success, negative integer otherwise

intel_vvp_warp_bypass 

int intel_vvp_warp_bypass(intel_vvp_warp_channel_t* channel, uint32_t bypass, uint32_t skip_ram_page, uint32_t width, uint32_t height
Description
Enable or disable video bypass where the input video displays as is without any processing
Arguments

channel – a valid pointer to initialized video processing channel

bypass – a nonzero value to enable video bypass, zero to disable

skip_ram_page – number of skip ram page to use after enabling or disabling bypass. The software uses the same page number for both input and output blank skip logic.

width, height – override output resolution if necessary. Both width and height have to be nonzero. Typically, use to match the input resolution when enabling video bypass.

Return value
Zero on success, negative integer otherwise

intel_vvp_warp_reset_skip_ram 

void intel_vvp_warp_reset_skip_ram(intel_vvp_warp_channel_t* channel, uint32_t skip_ram_page)
Description

Reset skip RAM page setting all values to zero.

Skip RAM pages are programmed as part of intel_vvp_warp_apply_transform(). Some use scenarios may require skip RAM to reset explicitly. This function allows for that

Arguments

channel – a valid pointer to initialized video processing channel

skip_ram_page – skip RAM page to reset

Return value
None

intel_vvp_warp_reset_input_skip_ram 

void intel_vvp_warp_reset_skip_ram(intel_vvp_warp_channel_t* channel, uint32_t skip_ram_page)
Description

Reset input skip RAM page setting all values to zero.

Skip RAM pages are programmed as part of intel_vvp_warp_apply_transform(). Some scenarios may require skip RAM to reset explicitly, which this function allows for

Arguments

channel – a valid pointer to initialized video processing channel

skip_ram_page – input skip RAM page to reset

Return value
None

intel_vvp_warp_check_easy_warp_capable 

int intel_vvp_warp_check_easy_warp_capable(intel_vvp_warp_channel_t* channel)
Description
Check if the channel can perform easy warp transforms
Arguments
channel – a valid pointer to initialized video processing channel
Return value
Zero if the channel can perform easy warp transforms, negative integer otherwise

intel_vvp_warp_set_easy_warp 

int intel_vvp_warp_set_easy_warp (intel_vvp_warp_channel_t* channel, uint32_t easy_warp)
Description
Apply an easy warp transformation to the input video
Arguments

channel – a valid pointer to initialized, easy warp capable video processing channel

easy_warp – desired easy warp transformation as 32-bit unsigned integer encoded in the following way:

31 3 2 1 0
Reserved Mirror Rotation
  • Bits 1:0 Rotation field can have the following values:
    • 00b – no rotation;
    • 01b – 90 degrees counter-clockwise rotation
    • 10b – 180 degrees rotation
    • 11b – 270 degrees counter-clockwise rotation
  • Bit 2: mirrors input video if set. If combined with a rotation the mirror is applied first.
Return value
Zero on success, negative integer otherwise

intel_vvp_warp_set_output_latency 

void intel_vvp_warp_set_output_latency (intel_vvp_warp_channel_t* channel, uint32_t clock_offset)
Description
Offset the warp output start-of-processing with the start-of-output by the specified number of system clock cycles. For more information, refer to Warp Low Latency.
Arguments

channel – a valid pointer to initialized video processing channel

clock_offset – number of system clock cycles by which to offset the output start-of-processing

Return value
None

intel_vvp_warp_get_channel_framebuffer_size 

void 
intel_vvp_warp_get_channel_framebuffer_size
(intel_vvp_warp_channel_t* channel)
Description
Get total size of RAM required for the channel frame buffers.
Arguments
channel - a valid pointer to initialized video processing channel
Return
Size of required RAM in bytes

intel_vvp_warp_get_debug_register 

uint32_t intel_vvp_warp_get_debug_register (intel_vvp_warp_instance_t* instance, uint32_t reg_offset)
Description
Read content of a warp debug and measurement register. Refer to Warp Debug and Measurement Registers.
Arguments

instance – pointer to initialized intel_vvp_warp_instance_t structure

reg_offset – zero based register offset. Use the following register offset macros for this argument:

Macro Value
INTEL_VVP_WARP_DEBUG_MEM_WR_QUEUES0 0
INTEL_VVP_WARP_DEBUG_MEM_WR_QUEUES1 1
INTEL_VVP_WARP_DEBUG_MEM_RD_QUEUES0 2
INTEL_VVP_WARP_DEBUG_MEM_RD_QUEUES1 3
INTEL_VVP_WARP_DEBUG_MEM_RD_CYCLES 8
INTEL_VVP_WARP_DEBUG_MEM_WR_CYCLES 9
INTEL_VVP_WARP_DEBUG_MEM_STALL_CYCLES 10
Return value
Current content of the warp debug and measurement register specified by the reg_offset argument

intel_vvp_warp_get_input_debug_register 

uint32_t intel_vvp_warp_get_input_debug_register (intel_vvp_warp_instance_t* instance, uint32_t input_idx, uint32_t reg_offset)
Description
Read content of a warp input debug and measurement register. Refer to Warp Debug and Measurement Registers.
Arguments

instance – pointer to initialized intel_vvp_warp_instance_t structure

input_idx – index of the warp IP input to access

reg_offset – zero based register offset. Use the following register offset macros for this argument:

Macro Value
INTEL_VVP_WARP_DEBUG_INPUT_FRAME_COUNT 0
INTEL_VVP_WARP_DEBUG_INPUT_FRAME_PERIOD 1
INTEL_VVP_WARP_DEBUG_INPUT_MEM_WRITES 2
INTEL_VVP_WARP_DEBUG_INPUT_MIPMAP_MEM_WRITES 3
Return value
Current content of the warp input debug and measurement register specified by the reg_offset argument

intel_vvp_warp_get_output_debug_register 

uint32_t intel_vvp_warp_get_output_debug_register (intel_vvp_warp_instance_t* instance, uint32_t output_idx, uint32_t reg_offset)
Description
Read content of a warp output debug and measurement register. Refer to Warp Debug and Measurement Registers.
Arguments

instance – pointer to initialized intel_vvp_warp_instance_t structure

output_idx – index of the warp IP output to access

reg_offset – zero based register offset. Use the following register offset macros for this argument:

Macro Value
INTEL_VVP_WARP_DEBUG_OUTPUT_FRAME_COUNT 0
INTEL_VVP_WARP_DEBUG_OUTPUT_FRAME_PERIOD 1
Return value
Current content of the warp output debug and measurement register specified by the reg_offset argument

intel_vvp_warp_get_engine_debug_register 

uint32_t intel_vvp_warp_get_engine_debug_register (intel_vvp_warp_instance_t* instance, uint32_t engine_idx, uint32_t reg_offset)
Description
Read content of a warp output debug and measurement register. Refer to Warp Debug and Measurement Registers.
Arguments

instance – pointer to initialized intel_vvp_warp_instance_t structure

engine_idx – index of the warp IP engine to access

reg_offset – zero based register offset. Use the following register offset macros for this argument:

Macro Value
INTEL_VVP_WARP_DEBUG_ENGINE_FRAME_COUNT 0
INTEL_VVP_WARP_DEBUG_ENGINE_FRAME_PERIOD 1
INTEL_VVP_WARP_DEBUG_ENGINE_BUSY_CYCLES 2
INTEL_VVP_WARP_DEBUG_ENGINE_FRAME_DELAY 3
INTEL_VVP_WARP_DEBUG_ENGINE_RUN_STATUS 4
INTEL_VVP_WARP_DEBUG_ENGINE_CACHE_LOADS 5
Return value
Current content of the warp engine debug and measurement register specified by the reg_offset argument

intel_vvp_warp_get_engine_status 

uint32_t intel_vvp_warp_get_engine_status (intel_vvp_warp_instance_t* instance, uint32_t engine_idx)
Description
Get current status flags of a warp engine. Refer to Warp Debug and Measurement Registers.
Arguments

instance – pointer to initialized intel_vvp_warp_instance_t structure

engine_idx – index of the warp IP engine to access

Return value
Current values of the engine status flags. The flags are in a 32 bit integer.
Bit Flag Description
0 Engine failed to complete frame A sticky flag indicating that the engine fails to complete the processing of a frame. The flag is cleared when read.

intel_vvp_warp_get_output_status 

uint32_t intel_vvp_warp_get_output_status (intel_vvp_warp_instance_t* instance, uint32_t output_idx)
Description
Get current status flags of the warp output. Refer to Warp Debug and Measurement Registers.
Arguments

instance – pointer to initialized intel_vvp_warp_instance_t structure

output_idx – index of the warp IP output to access

Return
Current values of the output status flags. The flags are in a 32 bit integer.
Bit Flag Description
0 Output frame has been repeated A sticky flag indicating that the output frame repeated because the next rendered frame does not complete in time. The IP clears the flag when read.

Data structures and types

intel_vvp_warp_base_t

Description
Platform specific type to perform register read and write operations on the warp IP. In bare metal environments such as a Nios V processor, it is defined as 32-bit unsigned integer representing physical address of the warp IP on the CPU bus

intel_vvp_warp_instance 

typedef struct intel_vvp_warp_instance
{
	intel_vvp_warp_base_t base;
	uint32_t num_inputs;
	uint32_t num_engines;
	uint32_t num_outputs;
} intel_vvp_warp_instance_t;
 
    
 
    

     Description
    
 
    

     Main data structure of the driver
    
 
    

     Members
    
 
    
 
     
base – warp IP access handler
 
     
num_inputs – number of available warp inputs
 
     
 num_engines – number of available warp engines
 
     
num_outputs – number of available warp outputs
 
    
 
   
 
  
 
  
 
   
  intel_vvp_warp_channel  
 
   
 
    
 
    
 
     
typedef struct intel_vvp_warp_channel
{
 uint32_t in_use;
 uint32_t idx;
 struct intel_vvp_warp_instance* instance;
 uint32_t num_engines;
 uint32_t ram_addr;
} intel_vvp_warp_channel_t
 
    
 
    

     Description
    
 
    

     Video processing channel resources and parameters structure
    
 
    

     Arguments
    
 
    
 
    

     Return value
    
 
    
 
     
in_use – non-zero value if the channel is allocated and initialized. Zero otherwise.
 
    
 
    
 
     
idx – index number of the channel
 
    
 
    
 
     
instance – pointer to the parent driver instance the channel belongs to
 
    
 
    
 
     
num_engines – number of warp engines for the channel
 
    
 
    
 
     
ram_addr - base address of RAM region allocated for the channel frame buffers
 
    
 
   
 
  
 
  
 
   
   intel_vvp_warp_channel_config   
 
   
 
    
 
    
 
     
typedef struct intel_vvp_warp_channel_config
{
 uint32_t ram_addr;
 intel_vvp_warp_cs_t cs;
  uint32_t width_input;
 uint32_t height_input;
 uint32_t width_output;
 uint32_t height_output;
 uint8_t lfr;
} intel_vvp_warp_channel_config_t
 
    
 
    

     Description
    
 
    

     Video processing channel configuration
    
 
    

     Members
    
 
    
 
     
ram_addr - base address of RAM region allocated for the channel frame buffers
 
    
 
    
 
     
cs – video color space. Must be initialized to 
 
     
     
      
  • 00b = YUV
    •  
      
  • 01b = RGB reduced range
    •  
      
  • 10b = RFG full range. 
    •  
     
 
    
 
    
 
     
width_input, height_input, width_output, height_output – input and output video dimensions
 
    
 
    
 
     
lfr – low frame rate fallback. Must be initialized to 0x0
 
    
 
   
 
  
 
  
 
   
 intel_vvp_warp_data 
 
   
 
    
 
    
 
     
typedef struct intel_vvp_warp_data
{
 uint32_t num_engines;
 const uint8_t* skip_ram_input;
 const uint8_t* skip_megablock_data;
 uint32_t skip_ram_page;
 uint32_t  mipmap_level;
 uint32_t mesh_step;
 intel_vvp_warp_engine_data_t engine_data[0];
} intel_vvp_warp_data_t;
 
    
 
    

     Description
    
 
    

     Warp data descriptor
    
 
    

     Members
    
 
    
 
     
num_engines – data for how many engines this set contains. .
 
    
 
    
 
     
skip_ram_input– data for input skip RAM. Generated by the intel_vvp_warp_data library. Refer to Warp Data structure.
 
    
 
    
 
     
skip_megablock_data – data for the blank skip logic. Generated by the intel_vvp_warp_data library. See WarpData structure.
 
    
 
    
 
     
_kip_ram_page – skip RAM page to use for blank skip logic for this transform. Warp IP provides 2 pages for intput and 2 pages for output blank skip logic. You can keep skip blank data for different transforms and switch between the pages as necessary. When a transform is applied the software uses the same page number for both input and output blank skip logic. 
 
    
 
    

     mipmap_level - maximum mipmap level used by the current transform. Must be in the range of 0..7
    
 
    

     mesh_step - mesh step in pixels used by the current transform. Must be 8 or 16.
    
 
    
 
     
engine_data – array of intel_vvp_warp_engine_data_t structures containing warp coefficients for each individual engine
 
    
 
   
 
  
 
  
 
   
 intel_vvp_warp_engine_data 
 
   
 
    
 
    
 
     
typedef struct intel_vvp_warp_engine_data
{
 uint32_t mesh_addr;
 uint32_t mesh_size;
 uint32_t filter_addr;
 uint32_t filter_size;
 uint32_t fetch_addr;
 uint32_t fetch_size;
 uint32_t start_h;
 uint32_t start_v;
 uint32_t end_h;
 uint32_t end_v;
 uint32_t mesh_stride;
} intel_vvp_warp_engine_data_t;
 
    
 
   
 
   
 
    

     Description
    
 
    

     Warp coefficient descriptor for an individual warp engine
    
 
    

     Members
    
 
    
 
     
mesh_addr – address of the mesh coefficients in memory
 
    
 
    
 
     
mesh_size – size of the mesh coefficients
 
    
 
    
 
     
filter_addr – address of the filter coefficients in memory
 
    
 
    
 
     
filter_size – size of the filter coefficients
 
    
 
    
 
     
fetch_addr – address of the fetch coefficients in memory
 
    
 
    
 
     
fetch_size – size of the fetch coefficients
 
    
 
    
 
     
start_h, start_v, end_h, end_v – engine processing region. Internally warp engine processes video in 16x8 pixel blocks with the top-left corner being block [0, 0]. The processing region is defined by the start and end block indexes in horizontal and vertical dimensions. 
 
    
 
    
 
     
mesh_stride – number of warp mesh nodes per mesh data row. (in sets of 4 minus 1). Required mesh stride is calculated by the intel_vvp_warp_data library. 
 
    
 
   
 
  
 
  
 
   
  intel_vvp_warp_data  
 
   
This software component uses transformation mesh in a predefined format to generate mesh, cache, and filter coefficient data required by the warp IP, and blank skip data if supported by the IP configuration. 
 
   
If two or four engines are available, the software splits workload evenly so that each engine processes a vertical section of the frame. This software component also provides a factory function to create a warp mesh object for the given input and output resolutions and IP configuration. 
 
   
 
    
 
     
      Table 1146.   intel_vvp_warp_data API reference
      
      
      
 
       Name 
       Description 
      
 
      
      
      
 
        WarpDataGenerator  
       Constructor of the intel_vvp_warp_data component 
      
 
      
 
        GenerateData  
       Generate warp data 
      
 
      
 
        GenerateLatencyParams  
       Generate recommended minimum latency settings for a given warp 
      
 
      
 
        GetLastErrorCode  
       Get warning or error code for the most recent call to GenerateData()  
      
 
      
 
        GetErrorString  
       Get a string describing the error code passed as argument 
      
 
      
    
 
   
 
   
 
    
 
     
      Table 1147.   intel_vvp_warp_data Helper functions
      
      
      
 
        Name  
        Description  
      
 
      
      
      
 
        GetHwContext  
       Create object containing warp IP parameters necessary to generate data 
      
 
      
 
        GenerateDriverData  
       Create and fill in warp data object required by the warp driver 
      
 
      
    
 
   
 
   
 
    
 
     
      Table 1148.   intel_vvp_warp_data Mesh factory function
      
      
      
 
        Name  
        Description  
      
 
      
      
      
 
         WarpMesh::Create   
       Create mesh object sufficient to hold transform data for the given input and output resolutions and IP configuration 
      
 
      
    
 
   
 
  
 
  
 
   
 WarpDataGenerator 
 
   
 
    
 
    
 WarpDataGenerator 
    
 
    

     Description
    
 
    

     Constructs the main object of the intel_vvp_warp_data software component. 
    
 
    

     Arguments
    
 
    

     None
    
 
    

     Return value
    
 
    

     None
    
 
   
 
  
 
  
 
   
  GenerateData  
 
   
 
    
 
    
 
     
WarpDataPtr GenerateData(const WarpDataContext& ctx, WarpMeshPtr& mesh)
 
    
 
    

     Description
    
 
    

     Generate warp coefficients using provided transformation mesh, video resolution and necessary IP parameters. If two or four warp engines are available, the workload is split evenly such that each engine processesa vertical section of the image 
    
 
    

     Arguments
    
 
    
 
     
ctx – reference to an instance of WarpDataContext object containing information about video resolution and IP parameters required to generate data 
 
    
 
    
 
     
mesh – pointer to the transformation mesh
 
    
 
    

     Return value
    
 
    

     On success the function returns a valid smart pointer to a WarpData object. If in any region of the frame the requested transform exceeds IP limitations such as maximum downscale ratio or block cache size, the region is rendered blank and the corresponding error code is set. You can retrieve the error code using GetLastErrorCode() call. 
    
 
   
 
  
 
  
 
   
GenerateLatencyParams
 
   
 
    
 
    
 
     
WarpLatencyParamsGenerateLatencyParams(const WarpDataContext& ctx, const WarpDataPtr warp_data, uint32_t system_clock, uint32_t video_clock, uint32_t full_height, uint32_t frame_rate)const
 
    
 
    

     Description 
    
 
    

     Generate recommended minimum warp latency settings for a given warp. The generated settings should be used to set up the video pipeline for the low latency processing. Refer to Low Latency. 
    
 
    

     Arguments
    
 
    

      ctx– reference to an instance of WarpDataContext object containing information about video resolution and IP parameters required to generate data 
    
 
    
 
     
warp_data– a smart pointer to a valid WarpData object
 
    
 
    
 
     
system_clock – system clock frequency
 
    
 
    
 
     
video_clock – video clock frequency
 
    
 
    
 
     
full_height – full output video height (including vertical blanking)
 
    
 
    
 
     
frame_rate – output frame rate
 
    
 
    

     Return value 
    
 
    
 
     
Initialized WarpLatencyParams object containing recommended minimum latency settings for the given warp 
 
    
 
   
 
  
 
  
 
   
 GetLastErrorCode 
 
   
 
    
 
    
 
     
 
      
uint32_t GetLastErrorCode()const
 
     
 
    
 
    

     Description
    
 
    

     Return error or warning code for the most recent call to GenerateData(). The software indicates if warp data generation fails or an important condition is detected by setting a numerical error code. Use this function to retrieve the most recent error code. 
    
 
    

     Arguments
    
 
    

     None
    
 
    

     Return value
    
 
    
 
     
Possible return values are:
 
     
 
      
 
       
        Table 1149.  Return Values
        
        
        
 
         Macro 
         Value 
         Description 
        
 
        
        
        
 
         Success 
         0 
         Data generated successfully 
        
 
        
 
         BlockCacheUsageHigh 
         1 
         Block cache usage too high. Output might be unstable 
        
 
        
 
         DataAllocError 
         2 
         Unable to allocate memory for the warp data 
        
 
        
 
         CompressionTooHigh 
         3 
         Software detected compression higher than 2:1 
        
 
        
 
         BlockCacheFull 
         4 
         Requested warp uses up all available block cache 
        
 
        
 
         FetchLogicError 
         5 
         Error detected in the block cache control logic 
        
 
        
 
         OutOfFetchMem 
         6 
         Requested warp requires too many block cache fetches 
        
 
        
 
         Unknown 
         7 
         All other errors 
        
 
        
      
 
     
 
    
 
   
 
  
 
  
 
   
 GetErrorString 
 
   
 
    
 
    
 
     
std::string GetErrorString(const uint32_t error_code)
          const
 
    
 
    

     Description
    
 
    

     Return string describing the error code obtained with GetLastErrorCode().
    
 
    

     Arguments
    
 
    

     error_code - integral error code value as returned by GetLastErrorCode()
    
 
    

     Return value
    
 
    

     An object of type std::string containing textual description of the error code
    
 
   
 
  
 
  
 
   
Data structures and types
 
  
 
  
 
   
  WarpMesh  
 
   
 
    
 
    
 
     
 using resolution_t = std::pair<uint32_t, uint32_t>;

class WarpMesh
{
public:
 static WarpMeshPtr Create(resolution_t& input, resolution_t& output, WarpHwContextPtr hw_ctx);
 uint32_t GetStep();
 uint32_t GetFractBits();
 uint32_t GetVNodes();
 uint32_t GetHNodes();
 uint32_t GetStreams();
 mesh_node_t* GetRow(uint32_t v);
}
 
    
 
    

     Description
    
 
    
 
     
Class containing user-defined transformation mesh.
 
    
 
    
 
     
 The transformation mesh defines a mapping between the output and input images. Each entry of the mesh (node) represents a position in the output image and contains the relevant x and y coordinates of the input image encoded as 32-bit integers. The step between mesh nodes and number of fractional bits in the 32-bit values are selected by the software based on the input and output resolution. If any of the dimensions exceeds the value of 3840 the software uses 16x16 mesh step with 3 fractional bits otherwise 8x8 mesh with 4 fractional bits is used. The WarpMesh class allows for multiple mesh streams to be encoded. However only single stream mesh is currently supported by the IP. The class automatically manages internal storage for the mesh data 
 
    
 
    

     Members
    
 
    

     Create(resolution_t& input, resolution_t& output, WarpHwContextPtr hw_ctx) – Factory method to create a mesh object.
    
 
    

     Argumenta
    
 
    
 
     
 sinput, output – input and output frame dimensions.
 
     
hw_ctx - smart pointer to an instance of WarpHwContext object containing relevant IP parameters
 
    
 
    

     Returns
    
 
    

     On success the function returns a valid smart pointer to a WarpMesh object. If requested input or output resolution exceeds current IP settings the null pointer is returned. 
     
uint32_t GetStep() - Returns distance between mesh nodes 
 
     
uint32_t GetFractBits() – Returns number of fractional bits in 32-bit position values
 
     
uint32_t GetVNodes()
 
     
uint32_t GetHNodes() - Returns number of vertical/horizontal nodes in the mesh respectively
 
     
mesh_node_t* GetRow(uint32_t v) - Returns pointer to the mesh row.Access individual nodes in the row using pointer arithmetic or indexing 
 
    
 
   
 
  
 
  
 
   
 mesh_node_t 
 
   
 
    
 
    
 
     
typedef struct mesh_node
{
 int32_t _x;
 int32_t _y;
} mesh_node_t
 
    
 
    

     Description
    
 
    

     Structure representing individual entry in the mesh
    
 
    

     Members
    
 
    

     _x, _y – coordinates of the input image this node maps to. the IP represents each value by a 32-bit signed integer with the four least significant bits containing fractional part for subpixel precision. 
    
 
   
 
  
 
  
 
   
 WarpMeshPtr 
 
   
 
    
 
    
 using WarpMeshPtr = std::shared_ptr<WarpMesh> 
    
 
    

     Description
    
 
    

     Type alias for a smart pointer wrapper around the mesh class
    
 
   
 
  
 
  
 
   
  WarpDataContext  
 
   
 
    
 
    
 
     
struct WarpDataContext
{
	WarpDataContext(const WarpHwContextPtr hw, uint32_t wi, uint32_t hi, uint32_t wo, uint32_t ho);
}


 
    
 
    

     Description
    
 
    

     Structure containing image dimensions and IP parameters required to generate data.
    
 
    

     Members
    
 
    
 
     
WarpDataContext(const WarpHwContextPtr hw, uint32_t wi, uint32_t hi, uint32_t wo, uint32_t ho) - Constructor. The constructor uses provided arguments to initialize the data members, which you should not modify. 
 
    
 
    

     Arguments
    
 
    
 
     
 hw – smart pointer to an instance of WarpHwContext object containing relevant IP parameters
 
    
 
    
 
     
 wi, hi – input image width and height
 
    
 
    
 
     
 wo, ho – output image width and height
 
    
 
   
 
  
 
  
 
   
 WarpData 
 
   
 
    
 
    
 
     
class WarpData
{
 virtual uint32_t _GetEngines() const;
 virtual const uint8_t* GetSkipRamInputData() const;
 virtual const uint8_t* GetSkipMegablockData() const;
 virtual const_WarpEngineData* GetEngineData(const uint32_t engine) const;
 virtual uint32_t GetLatencyLines() const;
 virtual uint32_t GetMipmapLevel() const;
 virtual uint32_t GetMeshStep() const;
};


 
    
 
    

     Description
    
 
    
 
     
Interface class for accessing generated warp coefficients and data
 
    
 
    

     Members
    
 
    
 
     
GetEngines() – returns the number of warp engine data objects. The value is always less or equal to MAX_ENGINES
 
    
 
    
 
     
GetSkipRamInputData() – returns pointer to the input skip RAM data
 
    
 
    
 
     
GetSkipMegablockData() – returns pointer to the skip blank logic data
 
    
 
    
 
     
GetEngineData() – returns pointers to individual WarpEngineData objects
 
    
 
    
 
     
GetLatencyLines() – returns latency in image lines of the current transform. This value is used by the GenerateLatencyParams() call to calculate warp latency settings 
 
     
GetMipmapLevel() – returns maximum mipmap level used by the current transform
 
     
GetMeshStep() – returns warp mesh step (8 or 16) used in this data set
 
    
 
   
 
  
 
  
 
   
  WarpEngineData  
 
   
 
    
 
    
 
     
class WarpEngineData
{
 virtual uint32_t GetMeshEntries() const;
 virtual uint32_t GetFilterEntries() const;
 virtual uint32_t GetFetchEntries() const;

 virtual const mesh_entry_t* GetMeshData() const;
 virtual const filter_entry_t* GetFilterData() const;
 virtual const fetch_entry_t* GetFetchData() const;
};

 
    
 
    

     Description
    
 
    

     Interface class for accessing data coefficients of individual warp engine
    
 
    

     Members
    
 
    
 
     
GetMeshEntries() – returns number of mesh entries in the data block
 
    
 
    
 
     
GetFilterEntries() – returns number of filter entries in the data block
 
    
 
    
 
     
 GetFetchEntries() – returns number of fetch entries in the data block
 
    
 
    
 
     
GetMeshData() – returns pointer to the mesh data
 
    
 
    
 
     
GetFilterData() – returns pointer to the filter data
 
    
 
    
 
     
GetFetchData() – returns pointer to the fetch data
 
    
 
   
 
  
 
  
 
   
  mesh_entry_t, filter_entry_t, fetch_entry_t  
 
   
 
    

     Description
    
 
    
 
     
Type aliases to use when accessing individual data blocks and calculating block data size in bytes.
 . 
    
 
   
 
  
 
  
 
   
 WarpLatencyParams 
 
   
 
    
 
    
 
     
struct WarpLatencyParams
{
 uint32_t _output_latency;
 uint32_t _total_latency;
};

 
    
 
    

     Description
    
 
    
 
     
Structure contains recommended pipeline latency settings for the low latency processing. Refer to Warp IP Latency. 
 
    
 
    

     Members
    
 
    
 
     
_output_latency - the recommended warp output clock offset to be used in intel_vvp_warp_set_output_latency() driver call. The value is in core_clock clock cycles 
 
     
_total_latency – the recommended minimum offset between the input and output frames. The value is in axi4s_vid_out_0_clock clock cycles 
 
    
 
   
 
  
 
  
 
   
 Helper functions 
 
  
 
  
 
   
 GetHwContext 
 
   
 
    
 
    
 
     
WarpHwContextPtr GetHwContext(intel_vvp_warp_channel_t* ch)
 
    
 
    

     Description
    
 
    

     Create object containing warp IP parameters necessary to generate data. Function uses warp channel driver structure to extract all necessary IP parameters and create object of the type WarpHwContext, required by the GenerateData() call 
    
 
    

     Arguments
    
 
    

     ch - valid pointer to initialized intel_vvp_warp_channel_t structure object mesh_set - reference to a set of transformation meshes 
    
 
    

     Return value
    
 
    

     On success the function returns a valid smart pointer to a WarpHwContext object. On failure a nullptr object is returned
    
 
   
 
  
 
  
 
   
  GenerateDriverData  
 
   
 
    
 
    
 
     
WarpDriverDataPtr GenerateDriverData(const WarpDataContext& ctx, const WarpDataPtr user_data, const uint32_t coef_base_address, const uint32_t skip_ram_page)
 
    
 
    

     Description
    
 
    
 
     
Create and fill in an object of type intel_vvp_warp_data_t required by the warp driver’s method intel_vvp_warp_apply_transform() to apply warp. 
 
    
 
    

     Arguments
    
 
    

     ctx - reference to the WarpDataContext object containing information about video resolution and parameters the IP uses to generate the warp data 
    
 
    

     user_data - Warp data as generated by the GenerateData() call
    
 
    

     coef_base_address - base address in the FPGA accessible RAM where the warp is placed.
    
 
    

     skip_ram_page - number of the blank skip ram page to use for this warp
    
 
    

     Return value
    
 
    

     On success the function returns a valid smart pointer to an intel_vvp_warp_data_t object. On failure a nullptr object is returned. Before applying the warp the client must still transfer the warp data to the locations specified in the returned intel_vvp_warp_data_t object 
    
 
   
 
  
 
  
 
   
 intel_vvp_warp_mesh 
 
   
This reference software component allows you to generate sample warp meshes for common affine transformations, perspective transformations, radial distortion compensation and arbitrary transforms defined by a set of curves. 
 
   
The main object of the component is WarpConfigurator. The  WarpConfigurator  provides the following three types of warp configurations that the host application can use independently.: 
 
   
 
   

    Figure 162. Fixed warp 
 In the fixed warp configuration a set of affine transformations such as translation, rotation, scaling, perspective correction as well as radial distortion (fisheye) compensation are configured individually using corresponding API calls. 
 
    
 
      
    
 
   
 
   

    Figure 163. 4x corner warp 
In the 4x corner configuration affine and perspective transformations are defined using four points positioned in or around the screen area; This configuration also allows to apply radial distortion compensation. 
 
    
 
      
    
 
   
 
   

    Figure 164. Arbitrary warp 
 Arbitrary transformation is defined by a set of curves controlled by a fixed number of control points (knots).
 
    
 
      
    
 
   
 
   
Warp meshes are tied to a specific input and output video resolution. The user must set these accordingly before generating a mesh. 
 
   
Offset, sizes and positions are accepted as absolute values in pixels. To allow for sub-pixel precision floating-point type is used. Internally these parameters normalized to the [0..1] range using current output resolution and kept in this form. The warp automatically fits into the new output resolution if it changes. 
 
   
 
    
 
     
      Table 1150.  intel_vvp_warp_mesh API reference
      
      
      
 
       Name 
       Description 
      
 
      
      
      
 
        WarpConfigurator  
       Constructor of the intel_vvp_warp_mesh component 
      
 
      
 
        SetInputResolution, GetInputResolution  
       Set or get input image resolution 
      
 
      
 
        SetOutputResolution, GetOutputResolution  
       Set or get output image resolution 
      
 
      
 
        GenerateMeshFromFixed  
       Generate mesh using fixed warp configuration 
      
 
      
 
        GenerateMeshFromCorners  
       Generate mesh using 4x corner warp configuration 
      
 
      
 
        GenerateMeshFromArbitrary  
       Generate mesh using arbitrary warp configuration 
      
 
      
 
        SetHSize, GetHSize  
       Set or get horizontal size of the image 
      
 
      
 
        SetVSize, GetVSize  
       Set or get vertical size of the image 
      
 
      
 
        SetHOffset, GetHOffset  
       Set or get horizontal offset of the image 
      
 
      
 
        SetVOffset, GetVOffset  
       Set or get vertical offset of the image 
      
 
      
 
        SetRotate, GetRotate  
       Set or get rotation angle 
      
 
      
 
        SetHMirror, GetHMirror  
       Set or get horizontal mirroring 
      
 
      
 
        SetVMirror, GetVMirror  
       Set or get vertical mirroring 
      
 
      
 
        SetZoom, GetZoom  
       Set or get zoom factor 
      
 
      
 
        SetHKeystone, GetHKeystone  
       Set or get horizontal keystone angle 
      
 
      
 
        SetVKeystone, GetVKeystone  
       Set or get vertical keystone angle 
      
 
      
 
        SetFOV, GetFOV  
       Set or get field of view 
      
 
      
 
        SetVAxisOffset, GetVAxisOffset  
       Set or get vertical axis offset 
      
 
      
 
        SetPreRadial, GetPreRadial  
       Set or get radial distortion compensation parameters 
      
 
      
 
        SetCorner, GetCorner  
       Set or get corner position 
      
 
      
 
        SetCornerNorm, GetCornerNorm  
       Set or get normalized corner position 
      
 
      
 
        SetArbitraryKnotsNum, GetArbitraryKnotsNum  
       Set or get size of the arbitrary control grid 
      
 
      
 
        SetArbitraryKnot, GetArbitraryKnot  
       Set or get position of arbitrary control knot 
      
 
      
 
        SetArbitraryKnotNorm, GetArbitraryKnotNorm  
       Set or get normalized position of arbitrary control knot 
      
 
      
 
        SetMaintainRatio, GetMaintainRatio  
       Set or get maintain aspect ratio setting 
      
 
      
 
        SetShrinkToFit, GetShrinkToFit  
       Set or get shrink to fit setting 
      
 
      
    
 
   
 
  
 
  
 
   
WarpConfigurator
 
   
 
    
 
    
 
     
WarpConfigurator(WarpHwContextPtr hw_ctx) 
 
    
 
    

     Description
    
 
    

     Constructs the main object of the intel_vvp_warp_mesh software component 
    
 
    

     Arguments
    
 
    

     hw_ctx - smart pointer to an instance of WarpHwContext object containing relevant IP parameters 
    
 
    

     Return value
    
 
    

     None
    
 
   
 
  
 
  
 
   
  SetInputResolution, GetInputResolution, SetOutputResolution, GetOutputResolution  
 
   
 
    
 
    
 
     
void SetInputResolution(const uint32_t width, const uint32_t height) void GetInputResolution(uint32_t& width, uint32_t& height) void SetOutputResolution(const uint32_t width, const uint32_t height) void GetOutputResolution(uint32_t& width, uint32_t& height)
 
    
 
    

     Description
    
 
    

     Set or get input and output image resolution
    
 
    

     Arguments
    
 
    
 
     
width – image width
 
    
 
    
 
     
height – image height
 
    
 
    

     Return value
    
 
    

     None
    
 
   
 
  
 
  
 
   
  GenerateMeshFromFixed, GenerateMeshFromCorners, GenerateMeshFromArbitrary  
 
   
 
    
 
    
 
     
WarpMeshPtr GenerateMeshFromFixed() WarpMeshPtr GenerateMeshFromCorners() WarpMeshPtr GenerateMeshFromArbitrary()
 
    
 
    

     Description
    
 
    

     Generate transformation mesh using fixed, 4x corners or arbitrary configurations respectively
    
 
    

     Arguments
    
 
    

     None
    
 
    

     Return value
    
 
    

     Smart pointer to the object of the type WarpMesh containing generated transformation mesh (please see intel_vvp_data interface section for the description of WarpMesh) 
    
 
   
 
  
 
  
 
   
 SetHSize, GetHSize, SetVSize, GetVSize 
 
   
 
    
 
    
 
     
void SetHSize(float pixels) float GetHSize() void SetVSize(float pixels) float GetVSize()
 
    
 
    

     Description
    
 
    

     Set or get horizontal and vertical size of the image, which is equivalent to scaling the image along the horizontal/vertical axis 
    
 
    

     Arguments
    
 
    

     pixels – horizontal or vertical size of the image accordingly
    
 
    

     Return value
    
 
    

     horizontal or vertical size of the image accordingly
    
 
   
 
  
 
  
 
   
  SetHOffset, GetHOffset, SetVOffset, GetVOffset  
 
   
 
    
 
    
 
     
void SetHOffset(float pixels) float GetHOffset() void SetVOffset(float pixels) float GetVOffset()
 
    
 
    

     Description
    
 
    

     Set or get horizontal and vertical offsets of the image
    
 
    

     Arguments
    
 
    

     pixels – horizontal or vertical offset of the image accordingly
    
 
    

     Return value
    
 
    

     horizontal or vertical offset of the image accordingly
    
 
   
 
  
 
  
 
   
  SetRotate, GetRotate  
 
   
 
    
 
    
 
     
void SetRotate(float angle) float GetRotate()
 
    
 
    

     Description
    
 
    

     Set or get rotation angle of the image in degrees. Image is rotated around the center
    
 
    

     Arguments
    
 
    

     angle – rotation angle in degrees
    
 
    

     Return value
    
 
    

     rotation angle in degrees
    
 
   
 
  
 
  
 
   
  SetHMirror, GetHMirror, SetVMirror, GetVMirror  
 
   
 
    
 
    
 
     
void SetHMirror(bool v) bool GetHMirror() void SetVMirror(bool v) bool GetVMirror()
 
    
 
    

     Description
    
 
    

     Set or get image mirroring along horizontal and vertical axis accordingly
    
 
    

     Arguments
    
 
    

     v – true to enable mirroring, false to disable
    
 
    

     Return value
    
 
    

     true if mirroring enabled, false otherwise
    
 
   
 
  
 
  
 
   
  SetZoom, GetZoom  
 
   
 
    
 
    
 
     
void SetZoom(float zoom) float GetZoom()
 
    
 
    

     Description
    
 
    

     Set or get image zoom value
    
 
    

     Arguments
    
 
    

     zoom – value > 1 to zoom in, < 1 to zoom out
    
 
    

     Return value
    
 
    

     Configured zoom value
    
 
   
 
  
 
  
 
   
  SetHKeystone, GetHKeystone, SetVKeystone, GetVKeystone  
 
   
 
    
 
    
 
     
void SetHKeystone(float angle) float GetHKeystone() void SetVKeystone(float angle) float GetVKeystone()
 
    
 
    

     Description
    
 
    

     Set or get horizontal and vertical keystone compensation angle accordingly
    
 
    

     Arguments
    
 
    

     angle - horizontal or vertical angle in degrees by which the projector is tilting relative to the normal to the projection surface. 
    
 
    

     Return value
    
 
    

     Horizontal or vertical projector tilting angle accordingly
    
 
   
 
   
 
 
  
 
  
 
   
  SetFOV, GetFOV  
 
   
 
    
 
    
 void SetFOV(float angle) float GetFOV() 
    
 
    

     Description
    
 
    

     Set or get field of View. Field of view represents projector’s beam angle. This value is necessary for correct keystone correction. The default value is 30° 
    
 
    

     Arguments
    
 
    

     angle - projector’s beam angle in degrees
    
 
    

     Return value
    
 
    

     Projector’s beam angle in degrees
    
 
   
 
   

    Figure 165. Field of View
    
 
      
    
 
   
 
  
 
  
 
   
  SetVAxisOffset, GetVAxisOffset  
 
   
 
    
 
    
 
     
void SetVAxisOffset(float v) float GetVAxisOffset()
 
    
 
    

     Description
    
 
    

     Set or get vertical offset of the optical axis from the normal to the projection plane. This value is required for correct keystone correction. Some projectors, particularly short throw models have their beam already at an angle to the wall. Take account of this initial angle when calculating keystone correction. The provided value is the absolute offset divided by the image height. The default value is 0 
    
 
    

     Arguments
    
 
    

     v - value of vertical axis offset
    
 
    

     Return value
    
 
    

     value of vertical axis offset
    
 
   
 
   

    Figure 166. Vertical Offset
    
 
      
    
 
   
 
  
 
  
 
   
  SetPreRadial, GetPreRadial  
 
   
 
    
 
    
 
     
void SetPreRadial(float x, float y, float k1, float k2) void GetPreRadial(float& x, float& y, float& k1, float& k2)
 
    
 
    

     Description
    
 
    

     Set or get radial distortion compensation parameters. The software uses Brown-Conrady distortion model
    
 
    

     Arguments
    
 
    
 
     
x, y – distortion center
 
    
 
    
 
     
 k1, k2 – 1st and 2nd distortion coefficients
 
    
 
    

     Return value
    
 
    

     None
    
 
   
 
  
 
  
 
   
  SetCorner, GetCorner  
 
   
 
    
 
    
 
     
void SetCorner(const ECornerId& corner, float pixel_x, float pixel_y) void GetCorner(const ECornerId& corner, float& pixel_x, float& pixel_y)
 
    
 
    

     Description
    
 
    

     Set or get position of an individual corner point of the 4x corner warp configuration
    
 
    

     Arguments
    
 
    
 
     
corner – corner identifier
 
    
 
    
 
     
pixel_x, pixel_y – horizontal and vertical coordinate of the corner
 
    
 
    

     Return value
    
 
    

     None
    
 
   
 
  
 
  
 
   
 SetCornerNorm, GetCornerNorm 
 
   
 
    
 
    
 
     
void SetCornerNorm(const ECornerId& corner, float x, float y) void GetCornerNorm(const ECornerId& corner, float& x, float& y)
 
    
 
    

     Description 
    
 
    
 
     
Set or get normalized position of an individual corner point of the 4x corner warp configuration
 
    
 
    

     Arguments
    
 
    
 
     
corner – corner identifier
 
     
x,y – horizontal and vertical coordinate of the corner in the range 0..1
 
    
 
    

     Return 
    
 
    
 
     
None
 
    
 
   
 
  
 
  
 
   
  SetArbitraryKnotsNum, GetArbitraryKnotsNum  
 
   
 
    
 
    
 
     
void SetArbitraryKnotsNum(uint32_t num) uint32_t GetArbitraryKnotsNum()
 
    
 
    

     Description
    
 
    

     Set or get number of control points (knots) for the arbitrary warp. Arbitrary warp is defined by a set of curves and control points arranged into NxN grid. This parameter sets the size of this grid. For simplicity the number of control points in both dimensions is the same 
    
 
    

     Arguments
    
 
    

     num – number of control knots in each dimension
    
 
    

     Return value
    
 
    

     number of control knots in each dimension
    
 
   
 
  
 
  
 
   
  SetArbitraryKnot, GetArbitraryKnot  
 
   
 
    
 
    
 
     
void SetArbitraryKnot(const uint32_t idx, const float pixel_x, const float pixel_y) 
void GetArbitraryKnot(const uint32_t idx, float& pixel_x, float& pixel_y)
 
    
 
    

     Description
    
 
    

     Set or get absolute position of individual control points. Points are numbered left to right, top to bottom
    
 
    

     Arguments
    
 
    
 
     
idx – zero based point index number
 
    
 
    
 
     
pixel_x, pixel_y – horizontal and vertical coordinate of the point
 
    
 
    

     Return value
    
 
    

     None
    
 
   
 
  
 
  
 
   
 SetArbitraryKnotNorm, GetArbitraryKnotNorm 
 
   
 
    
 
    
 
     
void SetArbitraryKnotNorm(const uint32_t idx, const float x, const float y) 
void GetArbitraryKnotNorm(const uint32_t idx, float& x, float& y)
 
    
 
    

     Description 
    
 
    
 
     
Set or get normalized position of individual control points. Points are numbered left to right, top to bottom
 
    
 
    

     Arguments
    
 
    
 
     
idx– zero based point index number
 
     
x,y – horizontal and vertical coordinate of the point in the range 0..1
 
    
 
    

     Return
    
 
    

     None
    
 
   
 
   
 
  
 
  
 
   
  SetMaintainRatio, GetMaintainRatio  
 
   
 
    
 
    
 
     
void SetMaintainRatio(bool val) bool GetMaintainRatio()
 
    
 
    

     Description
    
 
    

     Set or get maintain aspect ratio flag. If set the aspect ratio of the input resolution is preserved. As a result the output image may have blank areas along either horizontal or vertical axis 
    
 
    

     Arguments
    
 
    

     val – true to maintain input aspect ratio, false otherwise
    
 
    

     Return value
    
 
    

     Current maintain aspect ratio setting
    
 
   
 
  
 
  
 
   
 SetShrinkToFit, GetShrinkToFit 
 
   
 
    
 
    
 
     
void SetShrinkToFit(bool val) bool GetShrinkToFit()
 
    
 
    

     Description
    
 
    

     Set or get shrink to fit setting. If set the resulting image is scaled down after applying all transforms to make sure it fits into the screen. Otherwise the resulting image is cropped to fit output dimensions. This flag is only relevant for the Fixed warp configuration 
    
 
    

     Arguments
    
 
    

     val – true to shrink resulting image to fit output dimensions, false otherwise
    
 
    

     Return value
    
 
    

     Current shrink to fit setting
    
 
   
 
  
 
  
 
   
 Data structures and types 
 
  
 
  
 
   
 ECornerId 
 
   
 
    
 
    
 
     
enum ECornerId { 
ETopLeft = 0, 
ETopRight, 
EBottomLeft, 
EBottomRight, 
ETotalCorners, 
};
 
    
 
    

     Description
    
 
    

     Enum identifies individual corners in the 4x corner warp configuration
    
 
   
 
  
 
 
 
 
 
  
 
   
Section Content
   
 Using Warp IP Software
   
 Warp IP Software Code Examples
   
 
  
 
  

  

   Related Information
   
 
    
  
 
 
  


        
    

    

        
            Level Two Title