Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel® FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Text Box Intel® FPGA IP 43. Tone Mapping Operator Intel® FPGA IP 44. Test Pattern Generator Intel® FPGA IP 45. Unsharp Mask Intel® FPGA IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer Intel® FPGA IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO Intel® FPGA IP 51. Video Timing Generator Intel® FPGA IP 52. Vignette Correction Intel® FPGA IP 53. Warp Intel® FPGA IP 54. White Balance Correction Intel® FPGA IP 55. White Balance Statistics Intel® FPGA IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. Adaptive Noise Reduction Intel® FPGA IP x
10.1. About the Adaptive Noise Reduction IP 10.2. Adaptive Noise Reduction IP Parameters 10.3. Adaptive Noise Reduction IP Functional Description 10.4. Adaptive Noise Reduction IP Registers 10.5. Adaptive Noise Reduction IP Software API
10.1. About the Adaptive Noise Reduction IP x
10.1.1. Adaptive Noise Reduction IP Performance and Resources
10.3. Adaptive Noise Reduction IP Functional Description x
10.3.1. Adaptive Noise Reduction IP Interfaces
11. Advanced Test Pattern Generator Intel® FPGA IP x
11.1. About the Advanced Test Pattern Generator IP 11.2. Advanced Test Pattern Generator IP Parameters 11.3. Advanced Test Pattern Generator IP Functional Description 11.4. Advanced Test Pattern Generator IP Registers 11.5. Advanced Test Pattern Generator IP Software API
11.1. About the Advanced Test Pattern Generator IP x
11.1.1. Advanced Test Pattern Generator IP Performance and Resources
11.3. Advanced Test Pattern Generator IP Functional Description x
11.3.1. Test Patterns 11.3.2. Dimensions, Offsets, and Alpha Settings 11.3.3. Run-time Settings 11.3.4. Advanced Test Pattern Generator IP Interfaces
12. AXI-Stream Broadcaster Intel® FPGA IP x
12.1. About the AXI-Stream Broadcaster IP 12.2. AXI-Stream Broadcaster IP Parameters 12.3. AXI-Stream Broadcaster IP Interfaces
12.1. About the AXI-Stream Broadcaster IP x
12.1.1. AXI-Stream Broadcaster IP Features 12.1.2. AXI-Stream Broadcaster IP Performance and Resources
13. Bits per Color Sample Adapter Intel® FPGA IP x
13.1. About the Bits per Color Sample Adapter IP 13.2. Bits per Color Sample Adapter IP Parameters 13.3. Bits per Color Sample Adapter IP Dithering Functional Description 13.4. Bits per Color Sample Adapter IP Registers 13.5. Bits per Color Sample Adapter Software API
13.1. About the Bits per Color Sample Adapter IP x
13.1.1. Bits per Color Sample Adapter IP Performance and Resources
13.3. Bits per Color Sample Adapter IP Dithering Functional Description x
13.3.1. Bits per Color Sample Adapter IP Interfaces
14. Black Level Correction Intel® FPGA IP x
14.1. About the Black Level Correction IP 14.2. Black Level Correction IP Parameters 14.3. Black Level Correction IP Functional Description 14.4. Black Level Correction IP Registers 14.5. Black Level Correction IP Software API
14.1. About the Black Level Correction IP x
14.1.1. Black Level Correction IP Performance and Resources
14.3. Black Level Correction IP Functional Description x
14.3.1. Black Level Correction IP Interfaces
15. Black Level Statistics Intel® FPGA IP x
15.1. About the Black Level Statistics IP 15.2. Black Level Statistics IP Parameters 15.3. Black Level Statistics IP Interfaces 15.4. Black Level Statistics IP Registers 15.5. Black Level Statistics IP Software API
15.1. About the Black Level Statistics IP x
15.1.1. Black Level Statistics IP Performance and Resources
16. Chroma Key Intel® FPGA IP x
16.1. About the Chroma Key IP 16.2. Chroma Key IP Parameters 16.3. Chroma Key IP Interfaces 16.4. Chroma Key Replacement 16.5. Chroma Key IP Registers 16.6. Chroma Key IP Software API
16.1. About the Chroma Key IP x
16.1.1. Chroma Key IP Performance and Resources
17. Chroma Resampler Intel® FPGA IP x
17.1. About the Chroma Resampler IP 17.2. Chroma Resampler IP Parameters 17.3. Chroma Resampler IP Functional Description 17.4. Chroma Resampler IP Registers 17.5. Chroma Resampler IP Software API
17.1. About the Chroma Resampler IP x
17.1.1. Chroma Resampler Performance and Resources
17.3. Chroma Resampler IP Functional Description x
17.3.1. Chroma Resampler IP Interfaces
18. Clipper Intel® FPGA IP x
18.1. About the Clipper IP 18.2. Clipper IP Parameters 18.3. Clipper IP Interfaces 18.4. Clipper IP Registers 18.5. Clipper IP Software API
18.1. About the Clipper IP x
18.1.1. Clipper IP Performance and Resources
19. Clocked Video Input Intel® FPGA IP x
19.1. About the Clocked Video Input IP 19.2. Initializing the Clocked Video Input IP 19.3. Clocked Video Input IP Parameters 19.4. Clocked Video Input IP Interfaces 19.5. Clocked Video Input IP Registers 19.6. Clocked Video Input IP Software API
19.1. About the Clocked Video Input IP x
19.1.1. Clocked Video Input IP Features 19.1.2. Clocked Video Input IP Performance and Resources
20. Clocked Video to Full-Raster Converter Intel® FPGA IP x
20.1. About the Clocked Video to Full-Raster Converter IP 20.2. Clocked Video to Full-Raster Converter Parameters 20.3. Clocked Video to Full-Raster Converter Block Description 20.4. Clocked Video Converter to Full-Raster IP Registers
20.1. About the Clocked Video to Full-Raster Converter IP x
20.1.1. Clocked Video to Full-Raster Converter Features 20.1.2. Clocked Video to Full-Raster Converter Performance and Resources
20.3. Clocked Video to Full-Raster Converter Block Description x
20.3.1. Clocked Video to Full-Raster Converter Interfaces
21. Clocked Video Output Intel® FPGA IP x
21.1. About the Clocked Video Output IP 21.2. Clocked Video Output IP Parameters 21.3. Clocked Video Output IP Functional Description 21.4. Clocked Video Output IP Interfaces 21.5. Clocked Video Output IP Registers 21.6. Clocked Video Output IP Software API
21.1. About the Clocked Video Output IP x
21.1.1. Clocked Video Output IP Performance and Resources 21.1.2. Clocked Video Output IP Features
22. Color Plane Manager Intel® FPGA IP x
22.1. About the Color Plane Manager IP 22.2. Color Plane Manager IP Parameters 22.3. Color Plane Manager IP Functional Description 22.4. Color Plane Manager IP Registers 22.5. Color Plane Manager Software API
22.1. About the Color Plane Manager IP x
22.1.1. Color Plane Manager IP Performance and Resources
22.3. Color Plane Manager IP Functional Description x
22.3.1. Color Plane Manager IP Interfaces
23. Color Space Converter Intel® FPGA IP x
23.1. About the Color Space Converter IP 23.2. Color Space Converter IP Parameters 23.3. Color Space Converter IP Functional Description 23.4. Color Space Converter IP Registers 23.5. Color Space Converter IP Software API
23.1. About the Color Space Converter IP x
23.1.1. Color Space Converter IP Features 23.1.2. Color Space Converter IP Performance and Resources
23.3. Color Space Converter IP Functional Description x
23.3.1. Color Space Converter IP Interfaces
24. Defective Pixel Correction Intel® FPGA IP x
24.1. About the Defective Pixel Correction IP 24.2. Defective Pixel Correction IP Parameters 24.3. Defective Pixel Correction IP Functional Description 24.4. Defective Pixel Correction IP Registers 24.5. Defective Pixel Correction IP Software API
24.1. About the Defective Pixel Correction IP x
24.1.1. Defective Pixel Correction IP Performance and Resources
24.3. Defective Pixel Correction IP Functional Description x
24.3.1. Defective Pixel Correction IP Interfaces
25. Deinterlacer Intel® FPGA IP x
25.1. About the Deinterlacer IP 25.2. Deinterlacer Parameters 25.3. Deinterlacer IP Functional Description 25.4. Deinterlacer IP Registers 25.5. Deinterlacer IP Software API
25.1. About the Deinterlacer IP x
25.1.1. Deinterlacer Performance and Resources
25.3. Deinterlacer IP Functional Description x
25.3.1. Deinterlacer Interfaces
26. Demosaic Intel® FPGA IP x
26.1. About the Demosaic IP 26.2. Demosaic IP Parameters 26.3. Demosaic IP Functional Description 26.4. Demosaic IP Registers 26.5. Demosaic IP Software API
26.1. About the Demosaic IP x
26.1.1. Demosaic IP Performance and Resources
26.3. Demosaic IP Functional Description x
26.3.1. Demosaic IP Interfaces
27. FIR Filter Intel® FPGA IP x
27.1. About the FIR Filter 27.2. FIR Filter Parameters 27.3. FIR Filter IP Operation 27.4. FIR Filter Interfaces 27.5. FIR Filter Registers 27.6. FIR Filter IP Software API
27.1. About the FIR Filter x
27.1.1. FIR Filter IP Performance and Resources
27.3. FIR Filter IP Operation x
27.3.1. FIR Filter Processing 27.3.2. FIR Filter Precision 27.3.3. FIR Coefficient Specification 27.3.4. FIR Filter Symmetry 27.3.5. Result to Output Data Type Conversion
27.3.4. FIR Filter Symmetry x
27.3.4.1. No Symmetry 27.3.4.2. Horizontal Symmetry 27.3.4.3. Vertical Symmetry 27.3.4.4. Horizontal and Vertical Symmetry 27.3.4.5. Diagonal Symmetry
28. Frame Cleaner Intel® FPGA IP x
28.1. About the Frame Cleaner IP 28.2. Frame Cleaner IP Parameters 28.3. Frame Cleaner IP Functional Description 28.4. Frame Cleaner IP Interfaces 28.5. Frame Cleaner IP Registers 28.6. Frame Cleaner IP Software API
28.1. About the Frame Cleaner IP x
28.1.1. Frame Cleaner IP Performance and Resources
29. Full-Raster to Clocked Video Converter Intel® FPGA IP x
29.1. About the Full-Raster to Clocked Video Converter 29.2. Full Raster to Clocked Video Converter Parameters 29.3. Full-Raster to Clocked Video Converter Block Description 29.4. Full-Raster to Clocked Video Converter Registers
29.1. About the Full-Raster to Clocked Video Converter x
29.1.1. Full-Raster to Clocked Video Converter Features 29.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
29.3. Full-Raster to Clocked Video Converter Block Description x
29.3.1. Full Raster to Clocked Video Converter Interfaces
30. Full-Raster to Streaming Converter Intel® FPGA IP x
30.1. About the Full-Raster to Streaming Converter IP 30.2. Full-Raster to Streaming Converter Parameters 30.3. Full-Raster to Streaming Converter Block Description
30.1. About the Full-Raster to Streaming Converter IP x
30.1.1. Full-Raster to Streaming Converter Features 30.1.2. Full-Raster to Streaming Converter Performance and Resources
30.3. Full-Raster to Streaming Converter Block Description x
30.3.1. Full-Raster to Streaming Converter Interfaces
31. Genlock Controller Intel® FPGA IP x
31.1. About the Genlock Controller IP 31.2. Genlock Controller IP Parameters 31.3. Genlock Controller IP Functional Description 31.4. Using Genlock Controller IP Software 31.5. Genlock Controller IP Registers 31.6. Genlock Controller IP Software API
31.1. About the Genlock Controller IP x
31.1.1. Genlock Controller IP Performance and Resources
31.3. Genlock Controller IP Functional Description x
31.3.1. Genlock Controller IP Interfaces
31.4. Using Genlock Controller IP Software x
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 31.4.3. Setting the VCXO hold over 31.4.4. Restarting the Genlock Controller IP 31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 31.4.7. Disturbing a Reference Clock (a cable pull)
32. Generic Crosspoint Intel® FPGA IP x
32.1. About the Generic Crosspoint IP 32.2. Generic Crosspoint IP Parameters 32.3. Generic Crosspoint IP Interfaces 32.4. Generic Crosspoint IP Registers 32.5. Generic Crosspoint IP Software API
32.1. About the Generic Crosspoint IP x
32.1.1. Generic Crosspoint IP Features 32.1.2. Generic Crosspoint Performance and Resources
33. Genlock Signal Router Intel® FPGA IP x
33.1. About the Genlock Signal Router IP 33.2. Genlock Signal Router IP Parameters 33.3. Genlock Signal Router IP Interfaces 33.4. Genlock Signal Router IP Registers 33.5. Genlock Signal Router IP Software API
33.1. About the Genlock Signal Router IP x
33.1.1. Genlock Signal Router IP Features 33.1.2. Genlock Signal Router IP Performance and Resources
34. Guard Bands Intel® FPGA IP x
34.1. About the Guard Bands IP 34.2. Guard Bands IP Parameters 34.3. Guard Bands IP Interfaces 34.4. Guard Bands IP Registers 34.5. Guard Bands IP Software API
34.1. About the Guard Bands IP x
34.1.1. Guard Bands IP Performance and Resources
35. Histogram Statistics Intel® FPGA IP x
35.1. About the Histogram Statistics IP 35.2. Histogram Statistics IP Parameters 35.3. Histogram Statistics IP Interfaces 35.4. Histogram Statistics IP Registers 35.5. Histogram Statistics IP Software API
35.1. About the Histogram Statistics IP x
35.1.1. Histogram Statistics IP Performance and Resources
36. Interlacer Intel® FPGA IP x
36.1. About the Interlacer IP 36.2. Interlacer IP Parameters 36.3. Interlacer IP Functional Description 36.4. Interlacer IP Registers 36.5. Interlacer IP Software API
36.1. About the Interlacer IP x
36.1.1. Interlacer IP Performance and Resources
36.3. Interlacer IP Functional Description x
36.3.1. Interlacer IP Interfaces
37. Mixer Intel® FPGA IP x
37.1. About the Mixer IP 37.2. Mixer IP Parameters 37.3. Mixer IP Functional Description 37.4. Mixer IP Registers 37.5. Mixer IP Software API
37.1. About the Mixer IP x
37.1.1. Mixer IP Performance and Resources
37.3. Mixer IP Functional Description x
37.3.1. Mixer IP Interfaces
38. Pixels in Parallel Converter Intel® FPGA IP x
38.1. About the Pixels in Parallel Converter IP 38.2. Pixels in Parallel Converter IP Parameters 38.3. Pixels in Parallel Converter Interfaces 38.4. Pixels in Parallel Converter Registers 38.5. Pixels in Parallel Converter IP Software API
38.1. About the Pixels in Parallel Converter IP x
38.1.1. Pixels in Parallel Converter IP Performance and Resources
39. Scaler Intel® FPGA IP x
39.1. About the Scaler 39.2. Scaler IP Parameters 39.3. Scaler IP Functional Description 39.4. Scaler IP Registers 39.5. Scaler IP Software API
39.1. About the Scaler x
39.1.1. Scaler IP Performance and Resources
39.2. Scaler IP Parameters x
39.2.1. Scaler Maximum Resolution
39.3. Scaler IP Functional Description x
39.3.1. Coefficient Selection 39.3.2. Coefficient Quantization 39.3.3. Filter Behavior at Edge Boundaries 39.3.4. Partial Frame Scaling 39.3.5. 422 and 420 Chroma Sampled Data Scaling 39.3.6. Scaler IP Interfaces
39.3.1. Coefficient Selection x
39.3.1.1. Updating Scaler IP Runtime Coefficients
40. Stream Cleaner Intel® FPGA IP x
40.1. About the Stream Cleaner IP 40.2. Stream Cleaner IP Parameters 40.3. Stream Cleaner IP Functional Description
40.1. About the Stream Cleaner IP x
40.1.1. Stream Cleaner IP Performance and Resources
40.3. Stream Cleaner IP Functional Description x
40.3.1. Stream Cleaner IP Interfaces
41. Switch Intel® FPGA IP x
41.1. About the Switch IP 41.2. Switch IP Parameters 41.3. Switch IP Functional Description 41.4. Switch IP Registers 41.5. Switch IP Software API
41.1. About the Switch IP x
41.1.1. Switch IP Performance and Resources
41.3. Switch IP Functional Description x
41.3.1. Switch IP Latency 41.3.2. Switch IP Interfaces
42. Text Box Intel® FPGA IP x
42.1. About the Text Box IP 42.2. Text Box IP Parameters 42.3. Text Box IP Functional Description 42.4. Text Box IP Registers 42.5. Text Box IP Software API
42.1. About the Text Box IP x
42.1.1. Text Box IP Performance and Resources
42.3. Text Box IP Functional Description x
42.3.1. Writing Text at Run Time with Double Buffering 42.3.2. Writing Text at Run Time without Double Buffering 42.3.3. Text Box IP Interfaces
43. Tone Mapping Operator Intel® FPGA IP x
43.1. About the Tone Mapping Operator IP 43.2. TMO IP Parameters 43.3. TMO IP Block Description 43.4. TMO IP Registers 43.5. TMO IP Software API
43.1. About the Tone Mapping Operator IP x
43.1.1. TMO IP Features 43.1.2. TMO IP Performance and Resource Utilization
43.3. TMO IP Block Description x
43.3.1. TMO IP Interfaces 43.3.2. TMO IP Latency
44. Test Pattern Generator Intel® FPGA IP x
44.1. About the Test Pattern Generator IP 44.2. Test Pattern Generator IP Parameters 44.3. Test Pattern Generator IP Functional Description 44.4. Test Pattern Generator IP Registers 44.5. Test Pattern Generator IP Software API
44.1. About the Test Pattern Generator IP x
44.1.1. Test Pattern Generator IP Performance and Resources
44.3. Test Pattern Generator IP Functional Description x
44.3.1. Test Patterns 44.3.2. Output Subsampling and Color Space 44.3.3. Run-time Settings 44.3.4. Test Pattern Generator IP Interfaces
45. Unsharp Mask Intel® FPGA IP x
45.1. About the Unsharp Mask IP 45.2. Unsharp Mask IP Parameters 45.3. Unsharp Mask IP Functional Description 45.4. Unsharp Mask IP Registers 45.5. Unsharp Mask IP Software API
45.1. About the Unsharp Mask IP x
45.1.1. Unsharp Mask IP Performance and Resources
45.3. Unsharp Mask IP Functional Description x
45.3.1. Unsharp Mask IP Interfaces
46. Video and Vision Monitor Intel FPGA IP x
46.1. About the Video and Vision Monitor IP 46.2. Video and Vision Monitor IP Parameters 46.3. Video and Vision Monitor IP Functional Description 46.4. Video and Vision Monitor IP Registers 46.5. Video and Vision Monitor Software API
46.1. About the Video and Vision Monitor IP x
46.1.1. Video and Vision Monitor IP Performance and Resources
46.3. Video and Vision Monitor IP Functional Description x
46.3.1. Video and Vision Monitor IP Interfaces
47. Video Frame Buffer Intel® FPGA IP x
47.1. About the Video Frame Buffer IP 47.2. Video Frame Buffer IP Parameters 47.3. Video Frame Buffer IP Functional Description 47.4. Video Frame Buffer IP Registers 47.5. Video Frame Buffer IP Software API
47.1. About the Video Frame Buffer IP x
47.1.1. Video Frame Buffer Performance and Resources
47.3. Video Frame Buffer IP Functional Description x
47.3.1. Video Frame Buffer IP Interfaces
48. Video Frame Reader Intel FPGA IP x
48.1. About the Video Frame Reader IP 48.2. Video Frame Reader IP Parameters 48.3. Video Frame Reader IP Functional Description 48.4. Video Frame Reader IP Registers 48.5. Video Frame Reader IP Software API
48.1. About the Video Frame Reader IP x
48.1.1. Video Frame Reader IP Performance and Resources
48.3. Video Frame Reader IP Functional Description x
48.3.1. Video Frame Reader IP Interfaces
49. Video Frame Writer Intel FPGA IP x
49.1. About the Video Buffer Writer IP 49.2. Video Frame Writer IP Parameters 49.3. Video Frame Writer IP Functional Description 49.4. Video Frame Writer IP Registers 49.5. Video Frame Writer IP Software API
49.1. About the Video Buffer Writer IP x
49.1.1. Video Frame Writer IP Performance and Resources
49.3. Video Frame Writer IP Functional Description x
49.3.1. Video Frame Writer IP Interfaces
50. Video Streaming FIFO Intel® FPGA IP x
50.1. About the Video Streaming FIFO IP 50.2. Video Streaming FIFO IP Parameters 50.3. Video Streaming FIFO IP Interfaces
50.1. About the Video Streaming FIFO IP x
50.1.1. Video Streaming FIFO IP Performance and Resources
51. Video Timing Generator Intel® FPGA IP x
51.1. About the Video Timing Generator IP 51.2. Video Timing Generator IP Parameters 51.3. Video Timing Generator IP Functional Description 51.4. Video Timing Generator IP Interfaces 51.5. Video Timing Generator IP Registers 51.6. Video Timing Generator IP Software API
51.1. About the Video Timing Generator IP x
51.1.1. Video Timing Generator IP Features 51.1.2. Video Timing Generator IP Performance and Resources
52. Vignette Correction Intel® FPGA IP x
52.1. About the Vignette Correction IP 52.2. Vignette Correction IP Parameters 52.3. Vignette Correction IP Interfaces 52.4. Vignette Correction IP Registers 52.5. Vignette Correction IP Software API
52.1. About the Vignette Correction IP x
52.1.1. Vignette Correction IP Performance and Resources
53. Warp Intel® FPGA IP x
53.1. About the Warp IP 53.2. Warp IP Parameters 53.3. Warp IP Block Description 53.4. Warp IP Registers 53.5. Warp IP Software API
53.1. About the Warp IP x
53.1.1. Warp IP Features 53.1.2. Warp IP Performance and Resource Utilization
53.3. Warp IP Block Description x
53.3.1. Block Cache Tool 53.3.2. Warp IP Interfaces 53.3.3. Warp IP Latency 53.3.4. External Memory for Warp IP
53.5. Warp IP Software API x
53.5.1. Using Warp IP Software 53.5.2. Warp IP Software Code Examples
54. White Balance Correction Intel® FPGA IP x
54.1. About the White Balance Correction IP 54.2. White Balance Correction IP Parameters 54.3. White Balance Correction IP Functional Description 54.4. White Balance Correction IP Registers 54.5. White Balance Correction IP Software API
54.1. About the White Balance Correction IP x
54.1.1. White Balance Correction IP Performance and Resources
54.3. White Balance Correction IP Functional Description x
54.3.1. White Balance Correction IP Interfaces
55. White Balance Statistics Intel® FPGA IP x
55.1. About the White Balance Statistics IP 55.2. White Balance Statistics IP Parameters 55.3. White Balance Statistics IP Interfaces 55.4. White Balance Statistics IP Registers 55.5. White Balance Statistics IP Software API
55.1. About the White Balance Statistics IP x
55.1.1. White Balance Statistics IP Performance and Resources
56. Design Security x
56.1. Memory Subsystems 56.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel® FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Text Box Intel® FPGA IP
43. Tone Mapping Operator Intel® FPGA IP
44. Test Pattern Generator Intel® FPGA IP
45. Unsharp Mask Intel® FPGA IP
46. Video and Vision Monitor Intel FPGA IP
47. Video Frame Buffer Intel® FPGA IP
48. Video Frame Reader Intel FPGA IP
49. Video Frame Writer Intel FPGA IP
50. Video Streaming FIFO Intel® FPGA IP
51. Video Timing Generator Intel® FPGA IP
52. Vignette Correction Intel® FPGA IP
53. Warp Intel® FPGA IP
54. White Balance Correction Intel® FPGA IP
55. White Balance Statistics Intel® FPGA IP
56. Design Security
57. Document Revision History for Video and Vision Processing Suite User Guide

51.6. Video Timing Generator IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios II HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

intel_vvp_vtiming_get_param_vid_pid

prototype: 
 int intel_vvp_vtiming_get_param_vid_pid(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The product ID number

intel_vvp_vtiming_get_param_version_number

prototype: 
 int intel_vvp_vtiming_get_param_version_number(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The IP version number

intel_vvp_vtiming_get_param_num_pulses

prototype: 
 int intel_vvp_vtiming_get_param_num_pulses(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The NUM_PULSES parameter

intel_vvp_vtiming_get_param_output_is_cv

prototype: 
 int intel_vvp_vtiming_get_param_output_is_cv(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The OUTPUT_IS_CV parameter

intel_vvp_vtiming_get_param_aligned_only

prototype: 
 int intel_vvp_vtiming_get_param_aligned_only(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The ALIGNED_ONLY parameter

intel_vvp_vtiming_get_param_color_planes

prototype: 
 int intel_vvp_vtiming_get_param_color_planes(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The NUMBER_OF_COLOR_PLANES parameter

intel_vvp_vtiming_get_param_pip

prototype: 
 int intel_vvp_vtiming_get_param_pip(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The PIXELS_IN_PARALLEL parameter

intel_vvp_vtiming_get_param_bps

prototype: 
 int intel_vvp_vtiming_get_param_bps(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The BPS parameter

intel_vvp_vtiming_get_param_hsize

prototype: 
 int intel_vvp_vtiming_get_param_hsize(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The HSIZE parameter

intel_vvp_vtiming_get_param_vsize

prototype: 
 int intel_vvp_vtiming_get_param_vsize(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VSIZE parameter

intel_vvp_vtiming_get_param_cpu_clk_freq_hz

prototype: 
 int intel_vvp_vtiming_get_param_cpu_clk_freq_hz(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The CPU_CLK_FREQ_HZ parameter

intel_vvp_vtiming_get_param_build_hard_frame_lock

prototype: 
 int intel_vvp_vtiming_get_param_hard_frame_lock(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The BUILD_HARD_FRAME_LOCK parameter

intel_vvp_vtiming_get_param_build_soft_frame_lock

prototype: 
 int intel_vvp_vtiming_get_param_sof_frame_lock(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The BUILD_SOFT_FRAME_LOCK parameter

intel_vvp_vtiming_get_param_build_vrr

prototype: 
 int intel_vvp_vtiming_get_param_build_vrr(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The BUILD_VRR parameter

intel_vvp_vtiming_get_frame_start_pulse

prototype: 
 int intel_vvp_vtiming_get_frame_start_pulse(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The FRAME START IS PULSE field from REG_MODE register

intel_vvp_vtiming_set_frame_start_pulse

prototype: 
 int intel_vvp_vtiming_set_frame_start_pulse(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, setting this value forces the IP to generate the SOF as a short pulse, otherwise it is a toggle signal.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_out_is_blank

prototype: 
 int intel_vvp_vtiming_get_out_is_blank(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The BLANK_N_SYNC field from REG_MODE register

intel_vvp_vtiming_set_out_is_blank

prototype: 
 int intel_vvp_vtiming_set_out_is_blank(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, setting this value forces the IP to generate blank timing, otherwise it generates sync timing.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_allow_hv_reset

prototype: 
 int intel_vvp_vtiming_get_allow_hv_reset(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The HARDFRAMELOCK field from REG_MODE register

intel_vvp_vtiming_set_allow_hv_reset

prototype: 
 int intel_vvp_vtiming_get_allow_hv_reset(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, setting this value forces the IP to enable the hard frame lock.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_use_soft_reset

prototype: 
 int intel_vvp_vtiming_get_use_soft_reset(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The SOFTFRAMELOCK field from REG_MODE register

intel_vvp_vtiming_set_use_soft_reset

prototype: 
 int intel_vvp_vtiming_set_use_soft_reset(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, setting this value forces the IP to enable the soft frame lock.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_vrr

prototype: 
 int intel_vvp_vtiming_get_vrr(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VRR ENABLE field from REG_MODE register

intel_vvp_vtiming_set_vrr

prototype: 
 int intel_vvp_vtiming_set_vrr(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, setting this value forces the IP to enable the Variable Refresh Rate.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_vrr_linemode

prototype: 
 int intel_vvp_vtiming_get_vrr_linemode(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VRR LINE MODE field from REG_MODE register

intel_vvp_vtiming_set_vrr_linemode

prototype: 
 int intel_vvp_vtiming_set_vrr_linemode(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, setting this value forces the IP to enable the Variable Refresh Rate in line mode.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_hreset

prototype: 
 int intel_vvp_vtiming_get_tim_hreset(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The HRESET field from REG_RESET_POS register

intel_vvp_vtiming_set_tim_hreset

prototype: 
 int intel_vvp_vtiming_set_tim_hreset(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the expected horizontal position for the frame start input signal.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_vreset

prototype: 
 int intel_vvp_vtiming_get_tim_vreset(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VRESET field from REG_RESET_POS register

intel_vvp_vtiming_set_tim_vreset

prototype: 
 int intel_vvp_vtiming_set_tim_vreset(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the expected vertical position for the frame start input signal.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_htotal

prototype: 
 int intel_vvp_vtiming_get_tim_htotal(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The HTOTAL field from REG_TOTALS register

intel_vvp_vtiming_set_tim_htotal

prototype: 
 int intel_vvp_vtiming_set_tim_htotal(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the width of the raster

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_vtotal

prototype: 
 int intel_vvp_vtiming_get_tim_vtotal(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VTOTAL field from REG_TOTALS register

intel_vvp_vtiming_set_tim_vtotal

prototype: 
 int intel_vvp_vtiming_set_tim_vtotal(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the height of the raster

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_hb_end

prototype: 
 int intel_vvp_vtiming_get_tim_hb_end(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The HB_END field from REG_HB_END register

intel_vvp_vtiming_set_tim_hb_end

prototype: 
 int intel_vvp_vtiming_set_tim_hb_end(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the first active pixel after horizontal blanking

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_v{INDX}b_start where {INDX} goes from 1 to 2

prototype: 
 int intel_vvp_vtiming_get_tim_v{INDX}b_start(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The V{INDX}B START FIELD from REG_V{INDX}B_POS register

intel_vvp_vtiming_set_tim_v{INDX}b_start

prototype: 
 int intel_vvp_vtiming_set_tim_v{INDX}b_start(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the first line of vertical blanking for field {INDX}

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_v{INDX}b_end

prototype: 
 int intel_vvp_vtiming_get_tim_v{INDX}b_end(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The V{INDX}B END FIELD from REG_V{INDX}B_POS register

intel_vvp_vtiming_set_tim_v{INDX}b_end

prototype: 
 int intel_vvp_vtiming_set_tim_v{INDX}b_end(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the last line of vertical blanking for field {INDX}

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_f{INDX}_start where {INDX} goes from 1 to 2

prototype: 
 int intel_vvp_vtiming_get_tim_f{INDX}_start(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The FIELD {INDX} START from REG_FIELD_STARTS register

intel_vvp_vtiming_set_tim_f{INDX}_start

prototype: 
 int intel_vvp_vtiming_set_tim_f{INDX}_start(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the first line of field {INDX}

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_hs_start

prototype: 
 int intel_vvp_vtiming_get_tim_hs_start(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The HSYNC START from REG_HS_POS register

intel_vvp_vtiming_set_tim_hs_start

prototype: 
 int intel_vvp_vtiming_set_tim_hs_start(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the first pixel of the horizontal sync

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_hs_end

prototype: 
 int intel_vvp_vtiming_get_tim_hs_end(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The HSYNC END from REG_HS_POS register

intel_vvp_vtiming_set_tim_hs_end

prototype: 
 int intel_vvp_vtiming_set_tim_hs_end(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the first pixel after the horizontal sync

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_v{INDX}s_vstart where {INDX} goes from 1 to 2

prototype: 
int intel_vvp_vtiming_get_tim_v{INDX}s_vstart(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The V{INDX}SYNC VSTART from REG_V{INDX}S_START register

intel_vvp_vtiming_set_tim_v{INDX}s_vstart

prototype: 
 int intel_vvp_vtiming_set_tim_v{INDX}s_vstart(intel_vvp_vtiming_instance* instance, uint32_t in_val);argument:
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the first line of the vertical sync for field {INDX}

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_v{INDX}s_hstart

prototype: 
 int intel_vvp_vtiming_get_tim_v{INDX}s_hstart(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The V{INDX}SYNC HSTART from REG_V{INDX}S_START register

intel_vvp_vtiming_set_tim_v{INDX}s_hstart

prototype: 
 int intel_vvp_vtiming_set_tim_v{INDX}s_hstart(intel_vvp_vtiming_instance* instance, uint32_t in_val);argument:
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the first pixel of the vertical sync for field {INDX}

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_v{INDX}s_vend

prototype: 
 int intel_vvp_vtiming_get_tim_v{INDX}s_vend(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The V{INDX}SYNC VEND from REG_V{INDX}S_END register

intel_vvp_vtiming_set_tim_v{INDX}s_vend

prototype: 
 int intel_vvp_vtiming_set_tim_v{INDX}s_vend(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the last line of the vertical sync for field {INDX}

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_v{INDX}s_hend

prototype: 
 int intel_vvp_vtiming_get_tim_v{INDX}s_hend(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The V{INDX}SYNC HEND from REG_V{INDX}S_END register

intel_vvp_vtiming_set_tim_v{INDX}s_hend

prototype: 
 int intel_vvp_vtiming_set_tim_v{INDX}s_hend(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the first pixel after the vertical sync for field 1{INDX}

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_frame_start_jitter

prototype: 
 int intel_vvp_vtiming_get_frame_start_jitter(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The FRAME START MAX JITTER from REG_JITTER_CONT register

intel_vvp_vtiming_set_frame_start_jitter

prototype: 
 int intel_vvp_vtiming_set_frame_start_jitter(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the number of video clock cycles either side of the position of the expected start of frame

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_frame_adj_ignore

prototype: 
 int intel_vvp_vtiming_get_frame_adj_ignore(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The SOFT LOCK FRAME START IGNORE from REG_JITTER_CONT register

intel_vvp_vtiming_set_frame_adj_ignore

prototype: 
 int intel_vvp_vtiming_set_frame_adj_ignore(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, when you select True for Soft frame lock, this parameter specifies the number of lines where the frame start input signal is ignored

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_frame_adj_window

prototype: 
 int intel_vvp_vtiming_get_frame_adj_window(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The SOFT LOCK FRAME START ADJUST from REG_JITTER_CONT register

intel_vvp_vtiming_set_frame_adj_window

prototype: 
 int intel_vvp_vtiming_set_frame_adj_ignore(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, when you select True for Soft frame lock, this parameter specifies the total number of lines for soft lock, including the “ignore” lines.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_black_{INDX} where {INDX} goes from 0 to 3

prototype: 
 int intel_vvp_vtiming_get_black_{INDX}(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

REG_BLACK_{INDX} register

intel_vvp_vtiming_set_black_{INDX}

prototype: 
 int intel_vvp_vtiming_set_black_{INDX}(intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, the pixel value for color plane {INDX}.

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_start_counter

prototype: 
 int intel_vvp_vtiming_get_start_count(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The START COUNTER field from REG_FRAME_COUNTS register

intel_vvp_vtiming_get_frame_count

prototype: 
 int intel_vvp_vtiming_get_frame_count(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The FRAME COUNTER field from REG_FRAME_COUNTS register

intel_vvp_vtiming_get_actual_pixels_latched

prototype: 
 int intel_vvp_vtiming_get_actual_pixels_latched(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The FRAME LENGTH field from REG_FRAME_LENGTH register

intel_vvp_vtiming_get_tim_vtotal_latched

prototype: 
 int intel_vvp_vtiming_get_1_second_ltchd(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VTOTAL_ADJ field from REG_VTOTAL_ADJ register

intel_vvp_vtiming_get_1_second_ltchd

prototype: 
 int intel_vvp_vtiming_get_1_second_ltchd(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VIDCLKFREQ field from REG_VID_FREQ register

intel_vvp_vtiming_get_hv_reset_count

prototype: 
 int intel_vvp_vtiming_get_hv_reset(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The RESET COUNT field from REG_GENLOCK_STATS0 register

intel_vvp_vtiming_get_stable_count

prototype: 
 int intel_vvp_vtiming_get_stable_count(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The STABLE COUNT field from REG_GENLOCK_STATS0 register

intel_vvp_vtiming_get_inc_count

prototype: 
 int intel_vvp_vtiming_get_inc_count(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VTOTAL INC COUNTER field from REG_GENLOCK_STATS1 register

intel_vvp_vtiming_get_dec_count

prototype: 
 int intel_vvp_vtiming_get_dec_count(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The VTOTAL DEC COUNTER field from REG_GENLOCK_STATS1 register

intel_vvp_vtiming_get_tim_pulse{INDX}_hstart where {INDX} goes from 0 to 7

prototype: 
 int intel_vvp_vtiming_get_tim_pulse{INDX}_hstart(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The PULSE {INDX} HSTART field from REG_PULSE{INDX}_START register

intel_vvp_vtiming_set_tim_pulse{INDX}_hstart

prototype: 
 intel_vvp_vtiming_set_tim_pulse{INDX}_hstart (intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, sets the position of the first pixel of the pulse

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_pulse{INDX}_vstart

prototype: 
 int intel_vvp_vtiming_get_tim_pulse{INDX}_vstart(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The PULSE {INDX} VSTART field from REG_PULSE{INDX}_START register

intel_vvp_vtiming_set_tim_pulse{INDX}_vstart

prototype: 
 intel_vvp_vtiming_set_tim_pulse{INDX}_vstart (intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, sets the position of the first line of the pulse

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_pulse{INDX}_hend

prototype: 
int intel_vvp_vtiming_get_tim_pulse{INDX}_hend(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The PULSE {INDX} HEND field from REG_PULSE{INDX}_END register

intel_vvp_vtiming_set_tim_pulse{INDX}_hend

prototype: 
intel_vvp_vtiming_set_tim_pulse{INDX}_hend (intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, sets the position of the last pixel of the pulse

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

intel_vvp_vtiming_get_tim_pulse{INDX}_vend

prototype: 
 int intel_vvp_vtiming_get_tim_pulse{INDX}_vend(intel_vvp_vtiming_instance* instance);
argument:

instance, pointer to the intel_vvp_vtiming_instance

return value:

The PULSE {INDX} VEND field from REG_PULSE{INDX}_END register

intel_vvp_vtiming_set_tim_pulse{INDX}_vend

prototype: 
 intel_vvp_vtiming_set_tim_pulse{INDX}_vend (intel_vvp_vtiming_instance* instance, uint32_t in_val);
argument:

instance, pointer to the intel_vvp_vtiming_instance

in_val, sets the position of the last line of the pulse

return value:

if successful kIntelVvpVtimingOk, otherwise kIntelVvpVtimingInstanceErr

Related Information
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