Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 4/01/2024
Public

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PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING

Allows the Fitter to set the phase shift of a PLL output counter, and hence the phase shift of its generated clock, to improve timing for all edges affected by this clock. Apply multicycle timing exceptions to paths between the generated clock and other clocks in the design to avoid timing violations.

Type

Boolean

Device Support

  • Intel Agilex® 5
  • Intel Agilex® 7
  • Arria® 10
  • Cyclone® 10 GX
  • Stratix® 10

Notes

This assignment supports Fitter wildcards.

This assignment is included in the Fitter report.

Syntax

set_instance_assignment -name PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING -to <to> -entity <entity name> <value>