Visible to Intel only — GUID: QSF-MUX_RESTRUCTURE
Ixiasoft
Visible to Intel only — GUID: QSF-MUX_RESTRUCTURE
Ixiasoft
MUX_RESTRUCTURE
Allows the Compiler to reduce the number of logic elements required to implement multiplexers in a design. This option is useful if your design contains buses of fragmented multiplexers. This option repacks multiplexers more efficiently for area, allowing the design to implement multiplexers with a reduced number of logic elements. You can select the 'On' setting to minimize your design area; it will decrease logic element usage but may negatively affect design clock speed (fMAX). You can select the 'Off' to disable multiplexer restructuring; it does not decrease logic element usage and does not affect design clock speed (fMAX). You may select 'Auto' setting to allow the Quartus Prime software to determine whether multiplexer restructuring should be enabled. The Quartus Prime software uses other synthesis settings, for example, the Optimization Technique option, to determine if multiplexer restructuring should be applied to the design; the 'Auto' setting will decrease logic element usage but may negatively affect design clock speed (fMAX).
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- Intel Agilex® 5
- Intel Agilex® 7
- Arria® 10
- Cyclone® 10 GX
- Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MUX_RESTRUCTURE <value> set_global_assignment -name MUX_RESTRUCTURE -entity <entity name> <value> set_instance_assignment -name MUX_RESTRUCTURE -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name mux_restructure off set_instance_assignment -name mux_restructure on -to accel