Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 4/01/2024
Public

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FORCE_CLOCK_ENABLE_INFERENCE

Directs the Compiler to aggressively infer clock enables on the specified registers. Turning on this option helps to infer clock enables on registers even the compiler would not have otherwise done so. It might negatively impact the fitting since the number of clock enable signals available in a LAB is limited.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name FORCE_CLOCK_ENABLE_INFERENCE -entity <entity name> <value>
set_instance_assignment -name FORCE_CLOCK_ENABLE_INFERENCE -to <to> -entity <entity name> <value>

Example

set_instance_assignment -name force_clock_enable_inference on -to foo

See Also

Allow Synchronous Control Signals