Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 4/01/2024
Public

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Document Table of Contents

SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK

Identifies the signal as a base clock during gated clock conversion. Only has an impact if SYNTH_GATED_CLOCK_CONVERSION is also enabled.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK -entity <entity name> <value>
set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK -to <to> -entity <entity name> <value>

Example

set_instance_assignment -name synth_gated_clock_conversion_base_clock on -to foo

See Also

Auto Gated Clock Conversion