Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 4/01/2024
Public

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VERILOG_ALLOW_RAM_INFERRED_IN_GENERATE_LOOP

Allows the Compiler to infer RAMs in generate-for loops from Verilog Design Files. If this option is set to OFF, the Compiler defines RAMs in generate-for loops as regular logic.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Analysis & Synthesis report.

Syntax

set_global_assignment -name VERILOG_ALLOW_RAM_INFERRED_IN_GENERATE_LOOP <value>

Default Value

Off

Example

set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on